Defining Verilog-A vector in the maestro view

First of all, you asked this originally in the Feedback, Suggestions and Questions forum which is for issues with the forums, not for technical topics. So I moved this to an appropriate forum.

Please see this article: How to convert design variables which are spectre vectors to work with Explorer/Assembler

Andrew

First of all, you asked this originally in the Feedback, Suggestions and Questions forum which is for issues with the forums, not for technical topics. So I moved this to an appropriate forum.

Please see this article: How to convert design variables which are spectre vectors to work with Explorer/Assembler

Andrew

Hi Andrew,

Thank you for your prompt response. I'd like to clarify my query further. I need to input the specter vectors into the maestro simulation. Can you guide me on where exactly I should enter these vectors? Should they be placed in the design variables or in the parameter section? Additionally, do the three functions suggested in the article allow me the option to input the vector/string vector into maestro? If there's a way to override this in the maestro, that would be an ideal solution. If you could provide an example, it would be even more helpful. I appreciate your assistance.

Kind Regards,
Tom.

Hi Tom,

The code mentioned in that article was primarily to deal with the fact that in ADE L you could just enter the design variable value as [1 2 3 4] for example, but that doesn't work in ADE Explorer - the code would convert them into a syntax that works in ADE L. I pointed you to the article as it explained the workaround of using strcat - more detail below.

If (for example) you have a Verilog-A module that looks like this:

// VerilogA for mylib, vectorBlock, veriloga

`include "constants.vams"
`include "disciplines.vams"

module vectorBlock(op,ip);
output op;
input ip;
electrical op,ip;
parameter real num[3:0]={1,0,0,0};
parameter real den[3:0]={1,0,0,1};

analog begin
  $strobe("num: ",num[3],num[2],num[1],num[0]);
  $strobe("den: ",den[3],den[2],den[1],den[0]);
  V(op) <+ laplace_nd(V(ip),num,den);
end

endmodule

Then I might place an instance of this and set (on the instance):

num: mynum
den: myden

Then create two design variables in ADE Explorer:

mynum: strcat("[1 2 3 4]")
myden: strcat("[5 6 7 8]")

The strcat stuff is just a SKILL function to eventually produce [1 2 3 4] for the netlist. You might think "why can't I just put [1 2 3 4] - well, ADE Explorer doesn't see this as Spectre syntax and so it tries to evaluate it as SKILL (which is illegal). Surrounding with quotes alone isn't enough as otherwise ADE will just pass it as a string parameter to spectre (rather than a vector).

The resulting spectre netlist when you simulate it would be:

// Point Netlist Generated on: Sep 10 16:23:10 2023
// Generated for: spectre
// Design Netlist Generated on: Sep 10 16:23:10 2023
// Design library name: mylib
// Design cell name: testit
// Design view name: schematic
simulator lang=spectre
global 0
parameters temperature=27 mynum=[1 2 3 4] myden=[5 6 7 8]

// Library name: mylib
// Cell name: testit
// View name: schematic
R1 (b 0) resistor r=1K
R0 (a 0) resistor r=1K
V0 (a 0) vsource dc=1 type=dc
I1 (b a) vectorBlock num=mynum den=myden
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf 
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
saveOptions options save=allpub
ahdl_include "/export/home/forumuser/mylib/vectorBlock/veriloga/veriloga.va"

This will pass through the vectors to the Verilog-A model. The numbers themselves are nonsense in this case, but it's to show the principle.

Andrew