Gain margin and phase margin expressions from nyquist plots

Are you producing the nyquist plots by plotting the loop gain from a Spectre stb analysis? If not, how are you doing this?

Andrew

Hi again

I sorted it out by breaking it down to a few steps that need to be executed prior to phase margin calculation:

Find unity gain frequency:

ugf = cross(mag(getData("loopGain" ?result "stb")) "1" 1 "falling" nil nil nil)

save the real and imaginary parts of the loop gain:

real_lg = real(getData("loopGain" ?result "stb"))

imag_lg = imag(getData("loopGain" ?result "stb"))

Calculate the phase margin in degrees:

pm = ((180 / 3.14) * atan((value(imag_lg ugf) / value(real_lg ugf))))

Correct,

However, when using the pm/gm calculations from the stb analysis it says the circuit is unstable.

WARNING (SPECTRE-16922): Cannot obtain the phase margin and gain margin because the circuit is a positive feedback system and is unstable. This is because the magnitude of loopGain is greater than one at 112.202 Hz when the phase of loopGain crosses zero degree. To make the circuit stable, ensure that the magnitude of loopGain is less than one when the phase of loopGain crosses zero degree.

The circuit is an LDO regulator, so I sweep the load current to check for the stability at all load conditions. For some values of the load current, the phase starts at 180 and rolls down whereas for others, the phase starts at -180 and goes up (and then back down eventually)

These are the simulation results (it's an RC extracted view, so I used spectre X set in LX, as the GUI indicates this is a good setting for power management circuits). The load is steped down by halving it every 50us and running an stb at selected times. 

Dear unskilled,

Please allow me to add a few comments to your observation and your expression for phase margin from the loop gain.

1. Your observation that the conventional Tian's analysis for small-signal stability [1] does not always produce a result that is consistent with the observed transient response is one others have noted. If a system is not a minimum phase system (i.e. all poles in the LHP), the methodology may not produce an accurate stability result. This is documented in a few places, such in reference [2]. An LDO that uses an op-amp with a conventional compensation capacitor with little or no series resistance can form a non- minimum phase system. In your case, low currents that stress the stability combined with the lack of a compensating zero resistor, may have created a non-minimum phase case which can lead to an incorrect phase margin computation using Tien's methodology. In that case, the recommended strategy is to resort to a Nyquist analysis to validate stability. This is a favorite topic of Mr. Frank Wiemann, a frequent and highly valued contributor to this forum [3].

2. In your expression for phase margin, did you intent to subtract the result from 180 degrees? Specifically, if the measured loop phase at the 0 dB loop gain frequency is 180 degrees, does this not suggest the phase margin is 0 degrees and not 180 degrees? Graphically, from the ocean reference manual for the phaseMargin() function, Figure 1 details the definition.

3. Finally, I noticed your expression for phase margin does not unwrap the phase. Given the definition of phase margin, I believe you might want to use this function. In addition, I think you want to use the following:

pm (degrees) = 180 + value(phaseDegUnwrapped(imag_lg/real_lg) ugf)

Shawn

Figure 1

from page 525 of OCEAN Reference
Product Version ICADVM20.1
December 2021

[1]. M. Tian, V. Visvanathan, J. Hantgan and K. Kundert, "Striving for small-signal stability," in IEEE Circuits and Devices Magazine, vol. 17, no. 1, pp. 31-41, Jan. 2001, doi: 10.1109/101.900125

[2] Lee, T. (2003). The Design of CMOS Radio-Frequency Integrated Circuits (2nd ed.). Cambridge: Cambridge University Press. doi:10.1017/CBO9780511817281, page 452.

[3] Since I cannot include non-Cadence URL, do a search for "frankwiedmann loopgain"

Hi Shawn,

Thank you very much for your thorough reply and explanation. Let me elaborate a bit more:

1.This remains a bit fuzzy topic for me tbh. I'm testing the same circuit before and after parasitic extraction. Here you can see their gain and phase response. In the RC view there seems to be a pole somewhere around 50Hz that gets cancelled by a zero so gain flattens for a while again.

Prior to parasitics the system appears as a minimum phase system and both gain and phase look as expected. My initial expectation was to have somewhat degraded stability due to added second pole capacitance. I wonder if there's also a secondary signal path messing with the loop breaking point where I add my stability deep probe.

Below you can see the loop gain response for schematic and RC extracted. Here I can see why the phase unwraps.

2. What I do is simply calculate the "angle of attack" of the loop gain when crossing the unity circle. When doing the arc tangent, there's no need to unwrap anything as my answer is already an angle (i.e. phase margin from nyquist stability criterion), I just need to convert it from radians to degrees:

So there seems to be a degradation of few degrees, something I expected to happen. Using the expression presented above I can plot the phase margin vs. load current (not quite yet, there is an issue with the x-axis not matching).

The green curve is generated through the standard native pm calculation from the stb test in spectre (works fine for the schematic view), and the red one is using the arc tangent expression. For this particular corner, I see a phase margin degradation from low to mid load currents, and the minimum phase point shifts a bit (from 6 to 2mA approx), something expected as the total capacitance in critical nodes has changed.

I guess one can always do a step response to get the complete circuit behavior accounting for non-linearities as well, perhaps a 0 to worst-load step and max to worst-load step and look at the regulator response in several critical nodes.

Dear unskilled,

First, thank you for both reading my comments and expanding on your quandary!

A couple of thoughts in response to your added data regarding item [1]:

unSkilled said:

Prior to parasitics the system appears as a minimum phase system and both gain and phase look as expected. My initial expectation was to have somewhat degraded stability due to added second pole capacitance. I wonder if there's also a secondary signal path messing with the loop breaking point where I add my stability deep probe.

a. I don't know how you are compensating your opamp, but if you are using a conventional compensation capacitor and series resistor scheme, I am wondering if the fracturing that occurs of the compensation elements in the layout has introduced a more complex transfer response than in the "lumped element" version in your schematic view,

b. Are both the extracted view based netlist (RC) and schematic view based netlist driving the same load? I am sure you are aware of the significance of the load impedance on stability - especially at low load currents.

c. The other possibility that comes to mind is the pass transistor. Its physical layout may have much greater capacitance between its drain-source terminals than the schematic view presents. This capacitance also appears to contribute a zero that might be a factor

d. Finally, do you see the same difference between schematic netlist and extracted view based netlist open loop responses if you create a capacitance only (C-only) extracted view based netlist (i.e., only include the capacitive parasitics, not the trace resistances)? This may also suggest the source of the added zero/pole pair.

unSkilled said:

2. What I do is simply calculate the "angle of attack" of the loop gain when crossing the unity circle. When doing the arc tangent, there's no need to unwrap anything as my answer is already an angle (i.e. phase margin from nyquist stability criterion), I just need to convert it from radians to degrees:

I understand - thank you for clarifying this unskilled!

unSkilled said:

I guess one can always do a step response to get the complete circuit behavior accounting for non-linearities as well, perhaps a 0 to worst-load step and max to worst-load step and look at the regulator response in several critical nodes.

Speaking (wriiing?) for myself only, I always accompanied any small-signal stability analysis with a set of large signal (i.e., transient) simulations to validate the small-signal results. Usually, I would choose a couple of the corner cases [1] that showed the minimum amount of phase margin and run a set of transient analyses. A common technique was to mirror the conditions of the small-signal simulation in the transient analysis and impose a positive and negative load current impulse to the DC value and observe the transient response to each impulse.

Good luck! Tracking down those parasitics can be a challenge.

Shawn

[1] Simulations over silicon process, environment, temperature, and load type/load current