Seeking Clarification on Relxpert Aging Simulation Result

Dear Holz,

First, I must preface my remarks by noting my experience with reliability simulations is not with the Cadence reliability tool - but rather a similar tool that also runs in the Cadence Virtuoso environment. When I read some of your questions, however, they do not seem specific to the Cadence reliability tool, In fact, the results you included are similar to the type of reliability report which with I am somewhat familiar.

Holz said:

Does the result indicate that, specifically for HCI, the current degrades by 15% after 6.98e-10 year (around 0.1s)?

This is consistent with my understanding of the lifetime computation for a given amount of degradation. Clearly, the DC stress you have applied to the device are placing it under a large amount of HCI stress.

Holz said:

Does this result also imply a total current degradation of 156% over 1 year?

The aging rate for HCI is dependent on the conditions of the device and the device type (nmos/pmos) and hence not a constant (see Figure 1). Hence, I assume the tool has computed the Idsat degradation after 365 days in the stress conditions you have applied to it.

Holz said:

I went through the ADEL user guide, and it mentioned that the degradation criterion is calculated using the formula ΔIdsat / Idsat. However, if my circuit only operates in the linear region, would this model not be applicable?

HCI also impacts the threshold voltage (increases) and the gm (decreases). Hence, if your circuit is sensitive to these latter two parameters. it will undergo degradation. Referring once again to Figure 1, the rates of degradation are different for the two parameters Idsat and gm.

Holz said:

I'm unclear what does the term "Age" is calculated here. Considering I applied a DC voltage in the transient simulation (resulting in a duty cycle of 1), why is the outcome showing as 9.92e01?

My understanding  is that the "Age" term is a Cadence specific computation that is used to age a particular device after undergoing a stress simulation. In other words, for each device in a stress simulation, the value of Age is computed in order to "age" the device so that a second "performance" simulation using the aged device(s) can be performed to compare with the performance of a "fresh" device (one that has not undergone any aging).  My understanding of the Cadence Age term is based on a few reliability modeling papers - for example reference [2].

Holz said:

I've tried to display the results in ADEXL by plotting the drain current (/N0/d). However, the currents have no difference. Any insights on how to appropriately visualize this?

In order to see the impact of the aging, you need to apply the aging factors to the devices in your netlist to create an "aged netlist". You cannot simply view the results from your aging simulation to establish or view the degradation. Typically, the process to determine if a circuit meets its reliability requirement is a four step process:

1. Perform an initial "performance" simulation where you simulate and measure a critical circuit parameter.

2. Perform one or more stress simulations to determine the magnitude of the aging for each device in the netlist.

3. For each stress simulation, apply the aging factors for from that stress simulation to create an "aged netlist" for that stress case.

4. Repeat the performance simulation using each of the "aged netlists" and determine if change in the measured critical parameter results in a value that is within requirements.

Depending on the change in the critical parameter, you may need to modify the circuit to minimize the aging and repeat the above four steps.

Once again Holz, I must emphasize my comments are not based on a the Cadence tool you are using - so please verify any of them using Cadence documentation or customer support.

Shawn

Figure 1

from reference [1]

reference:

[1] Shihuan, Lin. “Hot-Carrier-Induced Current Degradation in Deep Sub-Micron MOSFETs from Subthreshold to Strong Inversion Region.” (2011).

[2] Xiaojun Li, Jin Qin, Bing Huang, Xiaohu Zhang and J. B. Bernstein, "A new SPICE reliability simulation method for deep submicrometer CMOS VLSI circuits," in IEEE Transactions on Device and Materials Reliability, vol. 6, no. 2, pp. 247-257, June 2006, doi: 10.1109/TDMR.2006.876572.

Hi Shawn,

many thanks for your insightful response. I truly appreciate the time and effort you took to provide such a detailed answer. I will certainly delve into the reference paper you've provided to deepen my understanding of the tool.

Hi Shawn,

many thanks for your insightful response. I truly appreciate the time and effort you took to provide such a detailed answer. I will certainly delve into the reference paper you've provided to deepen my understanding of the tool.

Dear Holz,

I just hope they help to clarify some of your questions! Often it is easy to lose track of the overall objective when the terms used are not clear...and in the reliability arena there are a lot of them! In addition, as I am sure you are aware, the topic is statistically based - which makes answers often difficult to assess. Good luck!

Shawn