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layout dependet effects in simulation

supriyo1985

Hi,

I am interested in simulating the layout-dependent effect (LDE). I have two different layouts where I want to observe the impact on threshold voltage caused by LDE. It appears that Cadence offers a DFM tool capable of simulating these effects, but I'm uncertain whether it is included with the Virtuoso license.

In the GXL layout environment, I couldn't locate a DFM tab. However, I did notice one under the TSMC PDK Tools (in attachment) on the virtuoso main window. I'm unsure about its functionality or whether that's the correct place to access this feature. Can anybody offer insights?

Regards

Supriyo

Parents

  • Dear Supriyo,

    supriyo1985 said:
    I am interested in simulating the layout-dependent effect (LDE). I have two different layouts where I want to observe the impact on threshold voltage caused by LDE. It appears that Cadence offers a DFM tool capable of simulating these effects, but I'm uncertain whether it is included with the Virtuoso license.


    In my experience with many MOS technologies, the layout dependent effects are included in the models - not a specific simulation option. The device models from a PDK for a given technology will include the impact of the proximity of a device feature to a nearby features and compute the impact on device parameters. As long as the PDK is supported by Cadence and includes layout dependent effects, the use of a netlist created from the extracted view a layout will include the impact of proximity effects.

    The DFM tool you are referring to is, in my understanding, used during layout to predict the impact of layout dependent (stress induced) effects on device current and matching. From the data sheet:

    "Virtuoso DFM performs a static check on the transistor layout to quantify the impact of layout- dependent effects on transistor current, and then excessive variations are flagged and reported to the layout designer for layout optimization.

    Virtuoso DFM also supports designer’s constraint-driven, layout-dependent- effect variability analysis. Designers
    verify that the layout meets intended matching constraints while layout is being constructed, and provide guidelines to drive layout modifications to mitigate the layout dependent effects."

    Hence, if you are interested specifically in quantifying the impact of your two layouts on the threshold voltage, I think you need to create an extracted view based netlist for each layout and simulate the two netlists in spectre.

    I do not work for Cadence, but this is my understanding. I am sure Cadence support can provide the most accurate answer to your question if you contact them.

    Shawn

  • in reply to ShawnLogan

    Thanks Shawn, it was helpful. 

  • in reply to supriyo1985

    Dear supriyo1985,

    You are most welcome - I was hoping I understood your questions enough to provide something of use to you!

    Shawn

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