As mentioned in the question, during the trans simulation, I found that the sum of node currents did not meet the KCL law when checking the trans operating point. I don't know why. Some people say it's parasitic diode current? May I ask how to look parasitic diode current? The pipe in the white box above flows through 5.18u, and the pipe in the white box below flows through 8.63u.
I print the transient operating point of five mosfet:M12-M87-M1-M3-M41 below，it seems that there is no leakage current from bulk.
And printed the current flowing into 5 MOS transistors at this node under transient conditions
One possible cause could be that the models are implemented as inline subckts with additional components around the MOSFET. The annotation of operating points (and printing of currents) could just be showing the operating point of the inline device rather than the true drain current (i.e. the current through the pin).
That said, the default behaviour for plotting the terminal current through the device pins is to plot the current through the subckt pin not the device pin (this is controlled by a spectre option, inlinesubcktcurrent, which defaults to subckt rather than device, although I guess it could have been changed in your environment or on the models themselves).
Another possible cause is to have a high conductance set for gmin, but that seems pretty unlikely as the differences are pretty high.
It's pretty unusual for Spectre to suffer from gross KCL errors because meeting KCL is one of the convergence criteria. Debugging this via screenshots (which are hard to read) in the forums without any knowledge of the PDK you're using is going to be pretty difficult, so I would strongly advise you contacting customer support (submit a support case after logging in).
Thank you for your reply. The PDK is tower .18um. Maybe this is a problem from PDK model. The spectre.out didn't seem to have an error. “Found trapezoidal ringing on node netxxx.” is because I give the input a step signal, such a prompt should be normal?
The trapezoidal ringing is not going to have anything to do with this - that's a common challenge with trapezoidal integration methods in all SPICE simulators with high gain circuits. It may not actually cause problems, and tightening the tolerances or switching to method=gear2only can fix that.
As for the PDK, there are a number of different Tower 0.18um technologies, and doing that investigation is something that should be done via customer support (I don't have the bandwidth to get hold of a PDK, build a test case and try it out myself; there would be too much back-and-forth and I answer here in my spare time).
So please contact customer support as I suggested earlier - that's the right way to investigate this.
SMaxwell said:As mentioned in the question, during the trans simulation, I found that the sum of node currents did not meet the KCL law when checking the trans operating point. I don't know why. Some people say it's parasitic diode current? May I ask how to look parasitic diode current? The pipe in the white box above flows through 5.18u, and the pipe in the white box below flows through 8.63u.
When I reviewed your operating point data and the manner in which the table displays the device name, a common issue came to mind. I am not sure if your netlist was composed using a schematic or layout based view (i.e., an extracted view). However, if it was composed from an extracted view, a common issue is that the operating point for a device may only represent one finger of a multiifinger device. In other words, suppose a device M100 has a size of 20 um/0.8 um and its layout is composed of 20 individual parallel devices of size 1 um/0.8 um. It is possible the name of the device M100 is associated with only a single finger of the device. Hence, if the total current in M100 is 100 uA, the reported operating point current for M100 is (1/20)*100 uA or 5 uA.
With that thought in mind, I took the 8.637 uA current shown in M12 (IM12) and the 5.18 uA current in M87 (IM87)and assumed that these represent the current in only one finger of the schematic device M12 and M87 respectively. Since I did not find the schematic widths of M12 nor M87 in your schematics nor in your text, I ran a simulation to determine what combinations of widths of M12 and M87 will yield a net current of zero to satisfy KCL.
Basically, i determined what combinations of:
(num_M12_fingers)*IM12 - (num_M87_fingers)*IM87
sum to approximately 0 uA.
The results are shown in Figure 1 where I show the matrix of the number of fingers of M12 (yellow shaded region) and of M87 (blue shaded region) and the sets that appear to satisfy KCL in the table below the blue and yellow shaded table. With reference to Figure 1, the combination of (3,5) (fingers of M12,fingers of M87) provide a near zero current:
3 * IM12 = 3 * 8.637 uA = 25.911 uA
5 * IM87 = 5 * 5.18 uA = 25.9 uA
A total of four combinations are shown that appear to meet KCL, but not knowing your exact device sizes a different set may apply in your schematic.
I thought I should at least pass this by you SMaxwell in case it is relevant to your observed behavior.
Thank you very much for coming up with a possible cause for this problem, and also for simulating it. I apologize for not posting the size before. The following two pictures will include the size of the MOSFET. It shouldn't be a problem with fingers, because my fingers are all 1, and it shouldn't be a problem with multiplier either, because the number multiplier of M12 and M87 are also 1。
I wondered whether you could plot (in your transient simulation) the current through all four terminals of M87? I just want to see whether the drain current matches the source current and whether there is (for some reason - not sure what it would be) any significant current through the bulk pin. I'd not noticed that the bulk of M87 is tied to the source, so potentially there could be current flowing through that.
Clutching at straws a little here - as I said, customer support is the best approach here.
The transient simulation of M87's four terminals is here. In circuit, the B of M87 is short to S.The PDK of Tower is provided by an agency in our country. Last time I asked a question and the agent did not respond, contacting customer support may not be helpful, unfortunately (emmmmm). Actually, this issue may not affect the overall circuit function, but I was quite confused when I saw this during the transient simulation
I'm not talking about Tower's support, I'm talking about Cadence's support. Anyway, thanks for showing those currents; sadly nothing obvious jumps out from that either.
SMaxwell said:The following two pictures will include the size of the MOSFET. It shouldn't be a problem with fingers, because my fingers are all 1, and it shouldn't be a problem with multiplier either, because the number multiplier of M12 and M87 are also 1
Well, I struck out on my first guess - sorry SMaxwell!
However, that forced me to study your posts more carefully. I believe I understand your observation after a little analysis.
I extracted the data from your posted graphic detailing the time domain behavior of the currents in M12 and M87. I also examined your hand-drawn schematic and now understand exactly what the role of M87 is in your circuit,
With reference to Figure 2, shown below, I attempted to replicate your time-domain simulation results for IM87 and IM12. In this plot at the top of Figure 2, you can clearly see the impact of the signal Vrp as it undergoes a negative edge transition. When it does, there is coupling of the signal to the source of M87 as a result of its gate-source capacitance. This causes the additional current flow in M87 between 5 us and about 5.2 us. After the coupled charge dissipates, the absolute value of the currents in M87 and M12 are essentially identical at about 5.18 uA and KCL is satisfied. In your operating point measurement, you measured the currents in M87 and M12 at the time at which the transient was present. The additional current in M87 over that in IM12 is the displacement current that is due to the coupled charge from its gate-source capacitance. In your time domain plot (and in the version I attempted to reproduce), you can see the impact of the edge transition of Vrp at 5 us in IM12 (as well as obviously in M87) and after that time until the transient charge is dissipated at about 5.2 us. This is all a result of the displacement currents which arise due to the transient nature of the signals across device capacitances.
Let me know your thoughts....
I'm sorry for the misunderstanding of the voltage source of Vrefp in the schematic diagram. In fact, the Vref in the schematic diagram is generated by the bias circuit. After the startup circuit is started, the bias voltage is constant. The reason why a voltage source is placed (you can see that the voltage source is shifted+deleted) is that I need to use the voltage source to determine the appropriate Vrefp, and then adjust the bias circuit to generate the voltage. I need to first explain the function of this circuit: the input stage of this circuit implements a constant Gm structure from input rail to rail, and the principle is a triple current mirror structure. The circuit adopts a 5V VDD, and the red line in the figure shows that when the input is close to the VDD, due to the closure of the P input pair, the current can flow through the Vrefp tube and flow through the triple current mirror to the N input pair. At this point, Gm=sqrt (2 * ID * un * Cox * W/L)=2gmn; Similarly, when the input approaches 0V, Gm=2gmp; Around VDD/2, Gm=gmn+gmp; Just make gmn=gmp, and Gm can achieve a constant Gm structure within the input voltage range of 0-5V. During the transient simulation process, only a step signal of 0-5V was added to Vin+, and Vin - and Vout (class AB as the output stage) were connected using unit gain negative feedback (buffer). The transient figure including Vrp(Vref) is below:And the circuit used comes from: A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries
Thank you for providing the additional details with regard to your reference voltage and the transient simulation!
I believe the same basic issue is still present - the 5 V signal applied at 5 us to the pmos devices whose gates are connected to Vin+ and Vin- couples to their common source node and injects charge that must be dissipated. This is a transient phenomena. If you are using an extracted view based netlist, there may be parasitic layout capacitances between the gate and source nodes of the two pmos whose gates are connected to Vin+ and Vin-. These will show displacement currents as the charge dissipates. The current through these capacitors are not flowing through the device terminals and hence an apparent KCL DC operating point confusion may arise.