Non satisfying KCL equation for virtuoso simulation operating point

Dear SMaxwell,

SMaxwell said:

The following two pictures will include the size of the MOSFET. It shouldn't be a problem with fingers, because my fingers are all 1, and it shouldn't be a problem with multiplier either, because the number multiplier of M12 and M87 are also 1

Well, I struck out on my first guess - sorry SMaxwell!

However, that forced me to study your posts more carefully. I believe I understand your observation after a little analysis.

I extracted the data from your posted graphic detailing the time domain behavior of the currents in M12 and M87. I also examined your hand-drawn schematic and now understand exactly what the role of M87 is in your circuit,

With reference to Figure 2, shown below, I attempted to replicate your time-domain simulation results for IM87 and IM12. In this plot at the top of Figure 2, you can clearly see the impact of the signal Vrp as it undergoes a negative edge transition. When it does, there is coupling of the signal to the source of M87 as a result of its gate-source capacitance. This causes the additional current flow in M87 between 5 us and about 5.2 us. After the coupled charge dissipates, the absolute value of the currents in M87 and M12 are essentially identical at about 5.18 uA and KCL is satisfied. In your operating point measurement, you measured the currents in M87 and M12 at the time at which the transient was present. The additional current in M87 over that in IM12 is the displacement current that is due to the coupled charge from its gate-source capacitance. In your time domain plot (and in the version I attempted to reproduce), you can see the impact of the edge transition of Vrp at  5 us in IM12 (as well as obviously in M87) and after that time until the transient charge is dissipated at about 5.2 us. This is all a result of the displacement currents which arise due to the transient nature of the signals across device capacitances.

Let me know your thoughts....

Shawn

Figure 2

...

I'm sorry for the misunderstanding of the voltage source of Vrefp in the schematic diagram. In fact, the Vref in the schematic diagram is generated by the bias circuit. After the startup circuit is started, the bias voltage is constant. The reason why a voltage source is placed (you can see that the voltage source is shifted+deleted) is that I need to use the voltage source to determine the appropriate Vrefp, and then adjust the bias circuit to generate the voltage. I need to first explain the function of this circuit: the input stage of this circuit implements a constant Gm structure from input rail to rail, and the principle is a triple current mirror structure. The circuit adopts a 5V VDD, and the red line in the figure shows that when the input is close to the VDD, due to the closure of the P input pair, the current can flow through the Vrefp tube and flow through the triple current mirror to the N input pair. At this point, Gm=sqrt (2 * ID * un * Cox * W/L)=2gmn; Similarly, when the input approaches 0V, Gm=2gmp; Around VDD/2, Gm=gmn+gmp; Just make gmn=gmp, and Gm can achieve a constant Gm structure within the input voltage range of 0-5V. During the transient simulation process, only a step signal of 0-5V was added to Vin+, and Vin - and Vout (class AB as the output stage) were connected using unit gain negative feedback (buffer). The transient figure including Vrp(Vref) is below:

And the circuit used comes from: A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries

Dear SMaxwell,

Thank you for providing the additional details with regard to your reference voltage and the transient simulation!

I believe the same basic issue is still present - the 5 V signal applied at 5 us to the pmos devices whose gates are connected to Vin+ and Vin- couples to their common source node and injects charge that must be dissipated. This is a transient phenomena. If you are using an extracted view based netlist, there may be parasitic layout capacitances between the gate and source nodes of the two pmos whose gates are connected to Vin+ and Vin-. These will show displacement currents as the charge dissipates. The current through these capacitors are not flowing through the device terminals and hence an apparent KCL DC operating point confusion may arise.

Shawn

Hi SMaxwell,

I want to echo what Andrew Beckett said:

t's pretty unusual for Spectre to suffer from gross KCL errors because meeting KCL is one of the convergence criteria. Debugging this via screenshots (which are hard to read) in the forums without any knowledge of the PDK you're using is going to be pretty difficult, so I would strongly advise you contacting customer support (submit a support case after logging in).

If there is a problem with Spectre (unlikely), customer support has direct access to R&D and can resolve your issue.   If it's a setup or PDK issue, they can also help.  That is the fastest way (and most accurate) to debug and resolve your issue.

best regards,

Tawna

Thank you for your suggestion. Seeking the instructor's consent for customer support is a difficult task, and I am ready to overlook the issue with this PDK model.