Hysteresis phenomenon in frequency tripler

The software I use is CentOS 7 64-bit ,TSMC 0.18 UM CMOS Mixed Signal RF General Purpose MiM FSG Al 1P6VM 1.8&3.3V

Dear Restart,

As I believe the authors of the paper you reference may have done from their plot, I think you just need to sweep the value of the tuning voltage using a staircase waveform (or equivalently apply a digital word to an ideal D/A converter) in both directions in a transient simulation. The dwell time at each step of the waveform is chosen by the amount of time required for the VCO frequency to settle within your desired accuracy. At the end of each step, measure the VCO output frequency over some time interval. The amount of time to remain at each step must be chosen to be a good number of VCO frequency time constants.

From the plot you included, it appears the control voltage is stepped in 100 mV increments between 0 V and 2.0 V for a total of 21 steps. I'm shown an example of what I think might be the two transient simulations (or one simulation where the negatively sloped ramp follows the positively sloped ramp) to use and the control voltage stimulus. I hope I understood your question and this provides you with some insight Restart.

Shawn

Figure 1

Dear Shawn,

If I do understand your way, You mean that actually the simulation time for each step of 100mv is not equal, either for 0 to 2V or 2 to 0V. And when the step increases, the simulation time needed decreases. Is that right? If that's it, how to I know what the amount of the simulation time for each step should be? I mean I do not get the point of what you say about "the amount of time required for the VCO frequency to settle within your desired accuracy". What do that mean?

Dear Restart,

Restart said:

If I do understand your way, You mean that actually the simulation time for each step of 100mv is not equal, either for 0 to 2V or 2 to 0V. And when the step increases, the simulation time needed decreases. Is that right?

I must have confused you Restart. The dwell time at each voltage step is intended to be the same. Referring to Figure 1, "tstep" is shown for the positively slope and negatively sloped waveforms. The initial time shown as "init_settling_time" is intended to be greater than "tstep" as I assume your VCO will require some time for its output frequency to settle to the desired accuracy before starting the control voltage stepped ramp. Hence, for each control voltage ramp, the total simulation time is:

"init_settling_time" + 20*"tstep"

A measurement is taken at the end of "init_settling_time" and at the end of each "tstep" to create a total of 21 measurements.

Does this make my figure and comments any clearer?

Restart said:

If that's it, how to I know what the amount of the simulation time for each step should be? I mean I do not get the point of what you say about "the amount of time required for the VCO frequency to settle within your desired accuracy". What do that mean?

When you change the control voltage, the output frequency will change significantly in the control voltage characteristic as the authors illustrate. The frequency does NOT change instantaneously and to estimate its value, you need to wait for it to settle to a final value. The longer you wait to make the frequency measurement, the greater the accuracy of the frequency measurement to the long term average at that control voltage. You can view the frequency settling behavior from a transient simulation if you measure the instantaneous frequency using the Calculator freq() function. Do not use the frequency() function as that will provide an average and you want to view the instantaneous frequency.

As an example of frequency settling for a VCO when undergoing a calibration procedure, please see Figure 2. Note that the settling time depends on the calibration step. Hence, you need to run a transient simulation and examine the frequency versus time plot of your VCO to determine how long each "tstep" needs to be to allow the frequency to settle to its desired accuracy (i.e., settled to with, for example, 1% of its final value).

I hope this makes some sense to you Restart.

Shawn

Figure 2

sorry, I still can't get your point. I think I can show you my settings so that possibly, you can show me your solution through my settings to let me get your point directly. Fig.1 is my tansient simution, which the total simulation time is 100ns. Fig.2 is DC simulation. And you mean that acutually the simulation I need to use is freq, but what I use is dft, which is shown as fig.3. The net11 is my output, which contributes to the resulit Fig.4. You mean that I should use the freq(), like fig5.?

fig.1

fig.2

fig.3

fig.4

fig.5

Dear Restart,

Restart said:

sorry, I still can't get your point. I think I can show you my settings so that possibly, you can show me your solution through my settings to let me get your point directly. Fig.1 is my tansient simution, which the total simulation time is 100ns. Fig.2 is DC simulation. And you mean that acutually the simulation I need to use is freq, but what I use is dft, which is shown as fig.3. The net11 is my output, which contributes to the resulit Fig.4. You mean that I should use the freq(), like fig5.?

1. You are not showing enough details about your transient simulation for 100 ns. My recommendation was that the transient simulation contain a staircase ramp function where the control voltage of your VCO takes 21 steps from 0V to 2V and then a second transient simulation where the control voltage of your VCO takes 21 steps from 2V to 0V. The time you dwell at each step ("tstep") must be long enough for the VCO frequency to settle to its final value.

In your example of a 100 ns, is the control voltage constant for the entire 100 ns?

2. You should use an errpreset of "conservative" and not "moderate" to provide a more accurate frequency measurement.

3. I do not recommend you use the dft() function to estimate the frequency. With only 1024 samples, the frequency estimate will be very inaccurate. You should use the freq() function as you shown in fig 5. This will plot the instantaneous frequency as a function of time. From that plot, you can determine how long it takes for your VCO frequency to settle for just this one control voltage in your simulation. You might be able to derive the time constant for your VCO settling time and use that to set the simulation time of each "tstep" in your two staircase ramp transient simulations.

Shawn

I realli feel sorry for replying for your help so long. I probably get your poimt. You mean that I may can use staircase ramp function through transient function. But I don't know how to reach staircase ramp function in transient simulation? Maybe what options? My other transient simulation settings are fig.1 and fig.2. Fig.1 is time step:maxstep 0.005n for 180nm process, and Fig.2 is algorithm for method:gear 2 only. Fig.3 is the differenc of dft and freq. I do not really know their difference.

fig.1

fig.2

fig.3

Dear Restart,

Restart said:

probably get your poimt. You mean that I may can use staircase ramp function through transient function. But I don't know how to reach staircase ramp function in transient simulation? Maybe what options?

You need to create the staircase waveform using a vpwl or a vapwlf source from the analogLib. You must enter the a set of time,voltage pairs to define the waveform as a piecewise linear waveform. You may do this entirely using the vpwl GUI, or alternatively, place the (x,y) pairs in a text file and place the path to the file in a vpwlf source,

Restart said:

My other transient simulation settings are fig.1 and fig.2. Fig.1 is time step:maxstep 0.005n for 180nm process, and Fig.2 is algorithm for method:gear 2 only.

I understand. Thank you.

Restart said:

Fig.3 is the differenc of dft and freq. I do not really know their difference.

You only have a limited number of frequency bins (512) from your expression for using the dft() function.  With a total sample time of 20 ns, you are sampling your waveform every 20 ns/1024 = 19.53 ps. This means that the period of your period measurement will have an uncertainty of about 20 ps. With a 5.3 GHz waveform (188 ps period), that represents a large potential error in your period estimate. In frequency terms, each frequency bin is 50 MHz. Hence, you cannot resolve a frequency using the dft() function to anything less than 50 MHz. For a 5.3 GHz frequency, 50 MHz represents a frequency error of 0.94% - which is a large number for many frequency measurements.

When you use the freq() function, you are using all the time points in your simulation. In your transient simulation GUI, you set the maximum time step to 5 ps. Hence, you period measurement will be accurate to well under 5 ps as the simulator will choose a value far less than than 5 ns to statisfy convergence criteria and then interpolate the result. Hence, your frequency measurement error using the freq() function will be far, far less than 0.94%.

I also annotated your frequency measurement to show how you must leave some time each time the control voltage undergoes a change in value. If you do not leave some time, the frequency of the VCO has not settled to its final value. You may use the expression for the freq() function in a second expression as I show to plot the frequency settling time in absolute terms (i.e., delatf/f). This can be used to select the proper value for "tstep" of your staircase waveform.

Shawn

Figure 4.

Sorry for replying for your help so long. I have replaced the DC voltage Vtune as vpwl, and the referenced settings are as fig.1. I just make a sample and ecpext to see the result as two “staircases”. One of that is for free running frequency when Vtune=1V, and the other one is for Vtune=2V. But the real result is as fig.2. I don’t know what wrong I get.

fig.１

fig.2

Dear Restart,

Restart said:

have replaced the DC voltage Vtune as vpwl, and the referenced settings are as fig.1. I just make a sample and ecpext to see the result as two “staircases”. One of that is for free running frequency when Vtune=1V, and the other one is for Vtune=2V.

It appears to me from your figure 1 that you did not create a staircase waveform. You created a linear ramp that starts at 0 with a value of 0 and linearly increases to 200 mV at 200 ns. Did you look at the simulated signal at the positive node of source V1?

Let's say you want to have a "tstep" and transition times of "ttran" and a voltage step of 100 mV. Then your pwl file (or the values in the GUI) need to be set to something like:

0.0, 0

0.0,(tstep - 0.50*ttran)

0.100,(tstep + 0.50*ttran)

0.100,(2*tstep - 0.50*ttran)

0.200,(2*tstep + 0.50*tran)

...

In your Figure 1, you only have 3 sets of x,y points and hence created a voltage ramp. In my example, 5 sets of x,y points are required to create steps of 0V, 100 mV, and 200 mV.

Restart said:

But the real result is as fig.2. I don’t know what wrong I get.

The plot you provided from the paper in your initial post suggests the VCO output frequency changes very little until a threshold control voltage is reached at which point the VCO frequency is changed significantly. Looking at your plot of frequency versus time and realizing your provided a control voltage ramp that is 200 mV at 200 ns, it appears the threshold voltage in your design may be close to 200 mV as the output frequency has suddenly reduced. Is not this the behavior you were trying to observe? Please see Figure 5.

Shawn

Figure 5

Dear Restart,

Restart said:

have replaced the DC voltage Vtune as vpwl, and the referenced settings are as fig.1. I just make a sample and ecpext to see the result as two “staircases”. One of that is for free running frequency when Vtune=1V, and the other one is for Vtune=2V.

It appears to me from your figure 1 that you did not create a staircase waveform. You created a linear ramp that starts at 0 with a value of 0 and linearly increases to 200 mV at 200 ns. Did you look at the simulated signal at the positive node of source V1?

Let's say you want to have a "tstep" and transition times of "ttran" and a voltage step of 100 mV. Then your pwl file (or the values in the GUI) need to be set to something like:

0.0, 0

0.0,(tstep - 0.50*ttran)

0.100,(tstep + 0.50*ttran)

0.100,(2*tstep - 0.50*ttran)

0.200,(2*tstep + 0.50*tran)

...

In your Figure 1, you only have 3 sets of x,y points and hence created a voltage ramp. In my example, 5 sets of x,y points are required to create steps of 0V, 100 mV, and 200 mV.

Restart said:

But the real result is as fig.2. I don’t know what wrong I get.

The plot you provided from the paper in your initial post suggests the VCO output frequency changes very little until a threshold control voltage is reached at which point the VCO frequency is changed significantly. Looking at your plot of frequency versus time and realizing your provided a control voltage ramp that is 200 mV at 200 ns, it appears the threshold voltage in your design may be close to 200 mV as the output frequency has suddenly reduced. Is not this the behavior you were trying to observe? Please see Figure 5.

Shawn

Figure 5

I apologize for the late reply.And excuse me, can you explain a bit about this code?

ShawnLogan said:

0.0, 0

0.0,(tstep - 0.50*ttran)

0.100,(tstep + 0.50*ttran)

0.100,(2*tstep - 0.50*ttran)

0.200,(2*tstep + 0.50*tran)

What does the 0.50*ttran mean? I mean, I know tstep and 2tstep are for 1^st point and 2^nd point, but why need plus or minus it?

Shall I still include the init_settling_time?

Dear Restart,

Restart said:

And excuse me, can you explain a bit about this code?

That is not code. Those are the time,value points for you to enter in your vpwl GUI. You only included three time,value points and they created a ramp waveform and not a staircase waveform. You are trying to generate a s staircase waveform. In this example for two steps, each step dwell time is "tstep". The transition times to go between 100 mV steps is ttran. See Figure 6 for an expanded view of the staircase waveform with the time,voltage pairs shown.

In Figure 7, I modified your vpwl GUI to allow for 5 time,value pairs and, using an example of tstep = 100 ns and ttran = 2 ns, show what the first three time,value pairs should be. When you change the number of time,value pairs from 3 to 5, two additional time, value pair boxes will appear to include the remaining time, value pairs using the values I show in my prior post.

Restart said:

What does the 0.50*ttran mean? I mean, I know tstep and 2tstep are for 1^st point and 2^nd point, but why need plus or minus it?

Please see the expanded view of the staircase waveform in Figure 6. One-half the transition time of ttran occurs before each time, voltage break point and one-half occurs after each time,voltage break point. ttran are the transition times to go from one control voltage value to the following control voltage value.

Restart said:

Shall I still include the init_settling_time?

Yes. I did not include a settling time in Figure 7, but it is straightforward to include an initial settling time prior to starting the staircase waveform.

Shawn

Figure 6

Figure 7

I apologize for the late reply and really thank for your help, since I get the breakthrough in the simulation. Fig.1 is the setting for initial time=30ns, and fig.2 is its correspoding result. Fig.3 is the setting for initial time=100ns, and fig.4 is its correspoding result. I feel curious about why the starting part of fig.1 is just "going up", but the one of fig.3 is a "narrow groove"?

And, does the tstep have to be only 100ns ,and the ttran have to be only 2ns?

fig.1

fig.2

fig.3

fig.4

Dear Restart,

It appears you are making progress - very good!

Restart said:

I feel curious about why the starting part of fig.1 is just "going up", but the one of fig.3 is a "narrow groove"?

I do not know the location of your signal /net1 shown in your freq() functional GUI. I was not able to find the node in your screenshots where the node names are shown. Hence, I do not know its behavior as your oscillator starts. I suspect, however, that the reason the two outputs of the freq() function differ initially in your latest figure 1 and figure 3 ViVA plots is related to your use of the "auto" Threshold mode and what signal /net1 is doing during oscillator start-up. Oscillator start-up relies on some source of noise to initiate oscillation. In a transient simulation, if you do not apply a stimuli to initiate oscillation, the noise source is numerical noise and hence will be somewhat random due to numerical noise (rounding or truncation...). With the Threshold Mode set to auto, the threshold is computed as the integrated value of the waveform divided by the range of integration. As the oscillator starts, however, its amplitude will be small and hence it may or may not cross the computed threshold or may cross one time and then only after several periods. This will not provide a good estimate of the frequency as the oscillator starts since the threshold value is the average value of the signal over the entire simulation and not the average value as it is starting.

This may be responsible for the two difference frequency measurements up to about 10 ns in your two simulations. You can check this by plotting /net1 for both simulations and comparing the two waveforms up to about 10 ns.

You might also consider setting the Threshold Mode to "User" and specifying what the threshold voltage of /net1. I don't think this will eliminate the difference between the freq() function outputs as the oscillator start-up process is not a deterministic process.

Restart said:

And, does the tstep have to be only 100ns ,and the ttran have to be only 2ns?

No. I only used those values as example settings. You should choose the best values for your oscillator. I outlined a way to estimate the frequency settling time in my prior response and show a means to create a waveform of relative frequency to view how long it takes the frequency to settle in my Figure 4 in that response. You set tstep to a value such that the oscillator frequency settles to whatever accuracy you want and then measure the frequency over a small time region at the end of tstep. So tstep consists of:

tstep = (t_settle) + (t_measure)

Clip waveform /net1 over t_measure and measure its average frequency.

Shawn

I apologize for the late reply, and may I ask about what does this mean?

ShawnLogan said:

tstep = (t_settle) + (t_measure)

I mean, may you make an example? An example for the setting of tstep by  (t_settle) + (t_measure)