Hysteresis phenomenon in frequency tripler

Dear Restart,

Restart said:

have replaced the DC voltage Vtune as vpwl, and the referenced settings are as fig.1. I just make a sample and ecpext to see the result as two “staircases”. One of that is for free running frequency when Vtune=1V, and the other one is for Vtune=2V.

It appears to me from your figure 1 that you did not create a staircase waveform. You created a linear ramp that starts at 0 with a value of 0 and linearly increases to 200 mV at 200 ns. Did you look at the simulated signal at the positive node of source V1?

Let's say you want to have a "tstep" and transition times of "ttran" and a voltage step of 100 mV. Then your pwl file (or the values in the GUI) need to be set to something like:

0.0, 0

0.0,(tstep - 0.50*ttran)

0.100,(tstep + 0.50*ttran)

0.100,(2*tstep - 0.50*ttran)

0.200,(2*tstep + 0.50*tran)

...

In your Figure 1, you only have 3 sets of x,y points and hence created a voltage ramp. In my example, 5 sets of x,y points are required to create steps of 0V, 100 mV, and 200 mV.

Restart said:

But the real result is as fig.2. I don’t know what wrong I get.

The plot you provided from the paper in your initial post suggests the VCO output frequency changes very little until a threshold control voltage is reached at which point the VCO frequency is changed significantly. Looking at your plot of frequency versus time and realizing your provided a control voltage ramp that is 200 mV at 200 ns, it appears the threshold voltage in your design may be close to 200 mV as the output frequency has suddenly reduced. Is not this the behavior you were trying to observe? Please see Figure 5.

Shawn

Figure 5

I apologize for the late reply.And excuse me, can you explain a bit about this code?

ShawnLogan said:

0.0, 0

0.0,(tstep - 0.50*ttran)

0.100,(tstep + 0.50*ttran)

0.100,(2*tstep - 0.50*ttran)

0.200,(2*tstep + 0.50*tran)

What does the 0.50*ttran mean? I mean, I know tstep and 2tstep are for 1^st point and 2^nd point, but why need plus or minus it?

Shall I still include the init_settling_time?

Dear Restart,

Restart said:

And excuse me, can you explain a bit about this code?

That is not code. Those are the time,value points for you to enter in your vpwl GUI. You only included three time,value points and they created a ramp waveform and not a staircase waveform. You are trying to generate a s staircase waveform. In this example for two steps, each step dwell time is "tstep". The transition times to go between 100 mV steps is ttran. See Figure 6 for an expanded view of the staircase waveform with the time,voltage pairs shown.

In Figure 7, I modified your vpwl GUI to allow for 5 time,value pairs and, using an example of tstep = 100 ns and ttran = 2 ns, show what the first three time,value pairs should be. When you change the number of time,value pairs from 3 to 5, two additional time, value pair boxes will appear to include the remaining time, value pairs using the values I show in my prior post.

Restart said:

What does the 0.50*ttran mean? I mean, I know tstep and 2tstep are for 1^st point and 2^nd point, but why need plus or minus it?

Please see the expanded view of the staircase waveform in Figure 6. One-half the transition time of ttran occurs before each time, voltage break point and one-half occurs after each time,voltage break point. ttran are the transition times to go from one control voltage value to the following control voltage value.

Restart said:

Shall I still include the init_settling_time?

Yes. I did not include a settling time in Figure 7, but it is straightforward to include an initial settling time prior to starting the staircase waveform.

Shawn

Figure 6

Figure 7

I apologize for the late reply and really thank for your help, since I get the breakthrough in the simulation. Fig.1 is the setting for initial time=30ns, and fig.2 is its correspoding result. Fig.3 is the setting for initial time=100ns, and fig.4 is its correspoding result. I feel curious about why the starting part of fig.1 is just "going up", but the one of fig.3 is a "narrow groove"?

And, does the tstep have to be only 100ns ,and the ttran have to be only 2ns?

fig.1

fig.2

fig.3

fig.4

Dear Restart,

It appears you are making progress - very good!

Restart said:

I feel curious about why the starting part of fig.1 is just "going up", but the one of fig.3 is a "narrow groove"?

I do not know the location of your signal /net1 shown in your freq() functional GUI. I was not able to find the node in your screenshots where the node names are shown. Hence, I do not know its behavior as your oscillator starts. I suspect, however, that the reason the two outputs of the freq() function differ initially in your latest figure 1 and figure 3 ViVA plots is related to your use of the "auto" Threshold mode and what signal /net1 is doing during oscillator start-up. Oscillator start-up relies on some source of noise to initiate oscillation. In a transient simulation, if you do not apply a stimuli to initiate oscillation, the noise source is numerical noise and hence will be somewhat random due to numerical noise (rounding or truncation...). With the Threshold Mode set to auto, the threshold is computed as the integrated value of the waveform divided by the range of integration. As the oscillator starts, however, its amplitude will be small and hence it may or may not cross the computed threshold or may cross one time and then only after several periods. This will not provide a good estimate of the frequency as the oscillator starts since the threshold value is the average value of the signal over the entire simulation and not the average value as it is starting.

This may be responsible for the two difference frequency measurements up to about 10 ns in your two simulations. You can check this by plotting /net1 for both simulations and comparing the two waveforms up to about 10 ns.

You might also consider setting the Threshold Mode to "User" and specifying what the threshold voltage of /net1. I don't think this will eliminate the difference between the freq() function outputs as the oscillator start-up process is not a deterministic process.

Restart said:

And, does the tstep have to be only 100ns ,and the ttran have to be only 2ns?

No. I only used those values as example settings. You should choose the best values for your oscillator. I outlined a way to estimate the frequency settling time in my prior response and show a means to create a waveform of relative frequency to view how long it takes the frequency to settle in my Figure 4 in that response. You set tstep to a value such that the oscillator frequency settles to whatever accuracy you want and then measure the frequency over a small time region at the end of tstep. So tstep consists of:

tstep = (t_settle) + (t_measure)

Clip waveform /net1 over t_measure and measure its average frequency.

Shawn

I apologize for the late reply, and may I ask about what does this mean?

ShawnLogan said:

tstep = (t_settle) + (t_measure)

I mean, may you make an example? An example for the setting of tstep by  (t_settle) + (t_measure)