INPUT OF CADENCE SCHEMATIC FROM CODE (SUCH AS VERILOG ETC)

Dear rtyuy,

rtyuy said:

i am designing 128*1 array design. want to give input to my circuit  not from pulse but externally from some Code, can you please help me is it possible to do so. if yes that what is the process.

If I understand your question, I assume you are interested in performing a conventional transient simulation and that your "Code" creates some type of waveform or waveforms versus time that you wish to use as stimuli to some nodes in your netlist.

There are at least three options that come to mind. Let me pass them by you in case either is relevant or of any interest.

1. Modify your "Code" to write the output waveform data to a text file (tab delimited, white space delimited or comma-separated variable based formats are acceptable) where each line contains a time value and the signal value. Include a vpwlf in your schematic for each waveform you wish to apply as an input stimuli with its output node connected to the input net of interest. In the GUI for the vpwlf, enter the path to the filename you created. This will use the text file generated by your "Code" as the output voltage of the vpwlf source.

2. Migrate your "Code" to verilog-A. Create a schematic symbol for your verilog-A code and instantiate it in your schematic. Connect the outputs of your verilog-A version of your "Code" to the respective inputs. I assume you will need to provide some type of clock input to your verilog-A block in order to advance the value of its outputs as time progresses. Hence, create a clock source using a vpulse (with a potential smoothing RC filter) and apply it as the clock input to your verilog-A block.

I'm sure there may be other options, but given your description, these two came to mind.

Shawn

thank you for replying ShawnLogan, yes you understand my question correctly. but i want to write a code in which i assign the inputs to nodes and then  fed that input to the circuit node. in short i want my first row activate for 1ns, then next row activate after 2ns  but for 1ns and so on upto 128th row. but  i not able to relate it to  "Hence, create a clock source using a vpulse (with a potential smoothing RC filter) and apply it as the clock input to your verilog-A block."

thank you for replying ShawnLogan, yes you understand my question correctly. but i want to write a code in which i assign the inputs to nodes and then  fed that input to the circuit node. in short i want my first row activate for 1ns, then next row activate after 2ns  but for 1ns and so on upto 128th row. but  i not able to relate it to  "Hence, create a clock source using a vpulse (with a potential smoothing RC filter) and apply it as the clock input to your verilog-A block."

This question is also very vague. Maybe you're using spectre, maybe using AMS (if AMS you could write a Verilog or SystemVerilog module to generate the stimulus; with Spectre you could use Verilog-A). Or you could use a vector file if you can pre-generate the stimulus as a set of changing logic inputs.

Expecting somebody to write some Verilog/Verilog-A code to do something for you is a bit optimistic, especially when you haven't actually described what you need (even if you had, it might be a lot of work for somebody - and everyone here is responding as a volunteer).

Andrew