Cadence Layout DRC Pins Error

Dear sarah1898,

Sarah1898 said:

however I keep getting this error that pins vout and vss are on the same net. I also put the extracted image through which I can see the issue in question when highlighting the vss metal wire. Why are they seen as one net even though there is poly in middle of active of both pmos?

I don't know the details of your technology, but I assume it is a single tub technology and, as such, all nmos devices share a common tub - the substrate. If I examine your schematic, you have connected node vout to the substrate of nmos device N4. However, this connects it to VSS as you have the substrate of nmos N3 also connected to VSS. To try to make it more clear, I annotated your schematic and attach it as Figure 1. In essence, you have both node vout and node VSS connected to the substrate. I am wondering, perhaps, if you intended to connect the bulk node of nmos N4 to node VSS and not node vout.

Shawn

Figure 1

Dear ShawnLogan,

Thank you for your reply! I guess I followed the below image in concept of connecting the 4th terminal of all my transistors where the source and body terminals are connected together. I didn't know about a common tub. If possible, could you please further explain the common tub of cadence to me? Is it not valid to always connect the source and body terminals of nmos and pmos transistors? Again, I really appreciate your help.

I am using ami06 technology library

Dear Sarah1898,

Sarah1898 said:

I didn't know about a common tub. If possible, could you please further explain the common tub of cadence to me? Is it not valid to always connect the source and body terminals of nmos and pmos transistors?

Sarah1898 said:

I am using ami06 technology library

I researched the ami06 technology library and found it is for the AMI C5N 0.5µ process. I also found a cross-section of the AMI C5N 0.5tµ echnology showing a pmos and an nmos transistor and have included it as Figure 2. If you examine the nmos device, its channel is formed in the p-substrate. Therefore, both its drain and source terminals must be at a potential of greater than or equal to the substrate in order to form a channel. Further all nmos devices share the same p-substrate as their "bulk" terminals . Therefore, all nmos devices have their substrate (bulk) terminals connected to ground. You may connect the source terminal of an nmos device to ground - which happens to be its substrate.terminal if you want.

However, if you examine the cross section of the pmos device, note that it resides in an n-well. The bulk terminal of a pmos device is not necessarily common to all pmos devices as there can be more than one n-well regions on a substrate. Therefore, if two pmos devices are NOT in the same n-well region, their bulk terminals can be connected to different voltages. However, to form a channel in a pmos device, the voltage of its bulk terminal must be greater than or equal to the voltage of its source and drain terminals.

In your schematic, you have the bulk terminal of nmos device N4 connected to circuit node vout. However, you also connected the bulk terminal of nmos device N3 to VSS. Since all nmos devices have a common bulk connection to the substrate, this connects circuit node vout to substrate ground - which is  VSS .

I hope this helps understand my comments a bit better.

Shawn

Figure 2

(from MOSIS)