deepprobe to access systemVerilog variables

Hello Andrew,

I am referring to a post which is locked:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/57152/deepprobe-to-access-veriloga#

I am trying to use your suggested model to probe an internal variable (which is inside a systemVerilog module) and connect it at the top level to a resistor.

I am using ADE Assembler, simulator=ams and I am figuring out how load the required command-line options in the GUI.

I created a file CommandLineOptions.scs with the following content:

-va,cgav_in_contrib

and I am trying to load that file doing

Test/RightMouseButton/Options/AMS simulator/

Include Option Settings/

Include Options Tab/

Files on xrun command line:  CommandLineOptions.scs

But this doesn't seem the correct location or the correct syntax.

I get the following error:

xrun: *E,SPCERR: The program encountered one or more errors while processing the input SPICE file(s) in the AMSD flow. For details, see the following messages.

amsspice: *    ERROR (SFE-874): "/.../env/CommandLineOptions.scs" 1:

Cannot run the simulation because syntax error `Unexpected operator "-"' was encountered at line 1, column 0. Correct the syntax error and rerun the simulation.

Thank you for your help!