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LVS says missing instance when the instance is there- Cadence Virtuoso Layout

mars32

Hello,

I am using Cadence Virtuoso Layout Suite XL.

I previously had a fine LVS but did xACT and made some changes and am now rerunning LVS, but it keeps telling me I have missing instances in layout. When I select these instances in schematic, they highlight the corresponding instance in layout, meaning it is connected. I have tried deleting one of the instances and then using the 'Update Component and Nets' to regenerate it, but I still get the same error in LVS.

I have checked the navigator, and it also appears under instances. 

I can't completely regenerate the entire circuit and I'm not sure what to do.

Thanks

  • So, to clarify: Virtuoso Layout 'Check Against Source' shows no errors but LVS fails...

    Check there are no 'ignore' properties on the devices.

    Cross-highlight/selection indicates the device binding. Connectivity could still be wrong, although you would get an error relating to that.

    If binding in doubt you could try 'Connectivity -> Update -> Binding'

    Also; be aware that devices can be ignored in Virtuoso (as referred to above) and filtered during LVS. Filtering rules are typically connectivity based to filter dummy or spare devices.

  • in reply to RobMan

    The Virtuoso Layout 'Check Against Source" does seem to show that my nets are connected.

    I tried the Connectivity -> Update -> Binding  but it still hasn't helped. I don't think there are any ignore properties. For example, I have 2 resistors giving me this missing instance issue but I have many others of the same kind that are fine.

    Do you have any other suggestions?

    Thanks

  • in reply to mars32

    'Check Against Source' is not just a connectivity check. It will check instance binding, master references, parameters, connectivity etc. Ensure you have all relevant checks enabled when you run.

    Virtuoso Layout XL layout connectivity is not "sign off". The LVS tool is. I suggest you use the LVS results to debug the design errors.

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