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nofill metalisation

Choayb

I have a problem with the LVS verification due to nofill metallization on the transmission lines.
are there any specific parameters to set in the LVS (pvs)?
so that it takes into account the connections between my circuit and the transmission lines I use?

  • By "nofill metalization" do you mean a 'no fill' layer to block metal fill in this region? I doubt this impact LVS in any way.

    This is not enough information. Missing connections? What sort of connections? What layers? What foundry PDK are you using? Is this specific to transmission lines or other devices too?

    Are the transmission lines marked as such in the layout? (a marker layer required, otherwise it's just a metal wire) i.e. Do the devices appear in the extracted netlist?

    If there are really missing connections (open circuits) use the PVS probing tool to identify where. This might help understand why.

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