unconnected pins in layout, pins not recognized

I build a padring which consists of library pads (XH018) that are only metal pads, with no esd protection components.

I split the padring into four cells, each representing one side of the package pads (JLCC68). Each side on its own passes DRC/LVS but with warnings. The warnings are "unconnected pins"

The pins are placed correctly, in MET1 TXT layer. How to fix these warnings?

As I said, on its own each side passes DRC/LVS with the above warnings, but if I add a pad with ESD components, that layout passes DRC/LVS without warnings. Clean.

Another thing is that if I assemble all four sides in one layout, I get a lot of mismatched nets

All these mismatched nets and instances are inside pads with ESD protection components. All of these unmatched nets and instances are suddenly inside the padring cell consisting of 12 pads which passes DRC/LVS clean on its own. The complete padring is connected via GND path in MET1 and there are contacts to substrate around the padring.

Any idea why suddenly the extraction is unable to match the instances?