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port connectivity in schematic generated by EMX blackbox

ashwinrs

Hi all, 

I am using Integrand EMX 6.2.0 with Virtuoso 6.1.7. I am trying to Blackbox transistors from EMX extraction (for a simple inverter having 10 fingers each for pMOS and nMOS). Upon completion of the EMX extraction, in the final schematic generated by EMX, all the transistor terminals are connected to the reference ground (GND), which is clearly not correct. To pinpoint the problem, I just took a schematic with one nMOS and tried blackboxing it. However, the schematic generated by the EMX simulator (once again) had all the MOS terminals shorted to the ground. 

How do I ensure correct connectivity to blackboxed cells while extraction? Please help. 

Product: Integrand EMX

Product Feature: EMX Simulation

Thanks,

Ashwin.

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