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Symbol 'patch' in lib 'basic' may lead to different LVS results in different IC suites?

LiQY20

Hello everyone,

I generated a digital module via Innovus and tried to import it into Virtuoso via Verilog and GDS file. I got two suites for IC design, one is Virtuoso 16.6+Calibre 2015, the other is Virtuoso 16.8+Calibre 2020. I found that using the latter one the LVS is clear, but using the foemer, there are errors. The schematics and layouts are precisely the same in two suites, for I just copied the Virtuoso files between them.

I tried to search for errors, and I found this symbol 'patch' in lib 'basic'. The schematics are just the same, but leading to different LVS results. 'Patch' symbol seems to be used for connecting two net with different names together, thus no layout, no electrical function. And I think the problem might lay there. Maybe different suites translate this patch's two ends in different ways, but I'm not sure whether this problem come from Calibre or Virtuoso.

I copied the extracted sch and layout extracted spice from the correct suite, and run comparison on the other, and it did pass.

What does the difference come from and how can I fix it. Assum that I'm sure this module is right and the LVS is wrong, how can I clear LVS in both suites? Or at least keep the two LVS results just the same.

Thank you all!

Parents

  • The patch component simply sets up an alias in the database between the two nets. During CDL netlisting (which is used for LVS), it should just netlist using one of the two names for all occurrences of either net within the subckt that's netlisted. I guess there might be a problem in Calibre if the name chosen for the pin is not the same as the name of the pin on the layout side.

    First of all, Calibre is not a Cadence tool - you probably need to get support from Siemens EDA on this.

    Also, those are not valid Virtuoso version numbers. I'm assuming you're actually talking about IC6.1.6 and IC6.1.8. If it works with the later versions, I'm not sure it makes sense to spend time trying to figure out why this doesn't work in a 9-year old versions of both the Cadence and Siemens EDA tools.

    Andrew

Reply

  • The patch component simply sets up an alias in the database between the two nets. During CDL netlisting (which is used for LVS), it should just netlist using one of the two names for all occurrences of either net within the subckt that's netlisted. I guess there might be a problem in Calibre if the name chosen for the pin is not the same as the name of the pin on the layout side.

    First of all, Calibre is not a Cadence tool - you probably need to get support from Siemens EDA on this.

    Also, those are not valid Virtuoso version numbers. I'm assuming you're actually talking about IC6.1.6 and IC6.1.8. If it works with the later versions, I'm not sure it makes sense to spend time trying to figure out why this doesn't work in a 9-year old versions of both the Cadence and Siemens EDA tools.

    Andrew

Children
  • in reply to Andrew Beckett

    Dear Andrew,

    I verified the problem does come from Calibre. Different versions of Calibre extracts different netlists when encountered 'patch' symbols.

    I still don't know how to extract a correct netlist via Calibre. However, I managed to flatten the netlist in Innovus so I can avoid using 'patch' symbol in schematic, and so the result is LVS is always clear. So I think this problem is solved.

    Thank you for your answer, Andrew.

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