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Ignore dummies in PVS using GPDK 45nm [solved]

hesaliveJim

I would like to Ignore dummies when performing LVS using PVS.

I'm using the virtual foundry GPDK 45nm (Cadence) to do some research.

I note in this post:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/58057/cdsenv-setting-with-backannotation-in-layoutxl/1393995#1393995

BrendaGray suggests:

lvsIgnore: When set to "true" or checked, it indicates that the dummy should be ignored during LVS checks.

This would do but I'm not sure where to place it within the PVS submission form:

I tried putting it in the Filter options shown above but it is complained and should it be lvsIgnore=TRUE wherever it's put?

I do know that a lot of designers recommend simply updating the schematic but as this is a 'virtual foundry' I see no harm -  in Calibre the option exist.

  • I don't have time right now to answer this properly, but I did want to say that I believe the post from BrendaGray was generated by something like ChatGPT (I did some searching at the time and found a number of other posts in other forums on totally different topics which also looked machine-generated). The text in that append is not entirely correct and it looks wrong in a way that only an LLM might produce rather than a real human!

    Andrew

  • So 'lvsIgnore' is a Virtuoso instance property. This is there to influence when to ignore devices relating to Virtuoso Layout Suite XL binding.

    'lvsIgnore' has no direct input into PVS LVS. It is not a rule command, setting or input into PVS LVS. It could however have some influence. Adding this property to a schematic instance and setting the value to true will inhibit netlisting of the instance to cdl. Typically the cdl netlist is used for LVS comparison. Hence with the schematic instance missing from the netlist it is not checked. This property has no bearing or influence on the extracted LVS layout netlist.

    Typically the addition of dummy devices results in these extra devices in the layout. If you choose not to backannotate these devices into the schematic for an LVS match then they need to be filtered from the check. A rule must be added to the PVS LVS rules to achieve this. Please see the the commands lvs_filter_option in

    Cadence PVS Developers Guide --

  • Good Lord first trolls now something AI, what next for us?

  • in reply to hesaliveJim
    hesaliveJim said:
    Good Lord first trolls now something AI, what next for us?

    When ChatGPT then starts trolling, then we'll be in trouble!

  • looking through the Cadence PVS Developers Guide as suggested by RobMan

    I created a file containing the line lvs_filter yes -mos as suggested on p849

    I then added the file  to the rules section of the LVS Run submission form shown in the original post

    and the layout matched therefore I think it worked.

    There might be a better way to do this but I'm happy for now.

  • in reply to hesaliveJim

    Glad that helped. Just be aware; 'lvs_filter' filters the devices under a range of connection conditions. You might want to be more specific to catch only the intended dummy devices. e.g. Only devices with all terminals shorted. 'lvs_filter_option' offers this option.

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