Stats

  • Locked Locked
  • Replies 0
  • Subscribers 125
  • Views 4350
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Problem with using a genvar in if statement in Verilog-a

Esmee Tackx
Dear 
I ran into some problems while I was trying to build a ring oscillator in verilog-a. 
RTL Code: 
// VerilogA for VerilogA_test, Test_interne_node, veriloga
 
`include "constants.vams"
`include "disciplines.vams"
 
module Test_interne_node(VDD, VSS, EN, out);
parameter integer N_stage = 3;
inout VDD, VSS;
input EN;
output out;
electrical out, VDD, VSS, EN;
electrical [N_stage:0] intern;
 
genvar i;
      for (i= 0; i <= N_stage-2; i=i+1) begin
            RDUC_INV I0(.VDD(VDD),.VSS(VSS),.In(intern[i]),.Out(intern[i+1]),.EN(EN));
            if (i == N_stage-2) begin
                  RDUC_INV I1(.VDD(VDD),.VSS(VSS),.In(intern[i+1]),.Out(out),.EN(EN));
                  //My_res #(.r(0)) R(.p(out),.n(intern[3]));
                  analog V(out,intern[0]) <+0;        // de spanning tussen deze twee nodes nul maken is ze in essentie korstluiten
            end
      end   
endmodule
The goal of the code is to build a ring oscillator using invertors I have designed using virtuoso schematic (called RDUC_INV). The code should link these oscillators in series and then feedback the last invertors output signal to the input of the first invertor, building a ring oscillator. The parameter N_stage is used so that there is a possibility to choose how big (3 invertors, 5 invertors, 7...) the oscillator can be and to be eventually used as a CDF parameter to be able to be swept while using assembler.
The problem with the code is that when using the genvar i in the if statements, it appears that i is always evaluated as zero even though it should change every run through the for loop. I tested out multiple cases to find out this is the problem
If the if statement says: if (i == N_stage-2) begin, the code inside the if statement is never executed; Whilst if the if statement says: if (i == 0) begin, the code in the if statement is executed every for loop. 
 
I have also tried using different versions of virtuoso (ic_6.1.8.310.rc, icadvm_20.10.310.rc) and they both show the problem. I have tried to work around the problem by using  generate statements, using a constant that counts with the loop but here there are problems cause there is no analog block. I also tried just having the code inside the if statement at the complete end outside of all the loops but this makes that I need to use the parameter N_stage as bus indicator in intern[]  (intern[N_stage]). The problem with this is that it doesn't' take the value of N_stage but it does some sort of memory read. I know this because when using this statement the nets of my design show for example to be inside[181567948] but this value changes every time the code is compiled without actually changing the code. 

I have added the schematic of the RDUC_INV invertor, the verilog-a file, the testbench with schematic and assembler file. 
https://kuleuven-my.sharepoint.com/:u:/g/personal/esmee_tackx_student_kuleuven_be/EWBU2IF07i5PhkRxmgpDfyIBUFifI96zSMWJRP6YwMkLzw?e=sZmUlQ 

Hopefully U can help me. 
Kind regards 
Esmee Tackx 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.