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New user - all inverter layout components getting one pin name

Hi all! I'm a new user for school and I'm trying to layout a simple inverter. When I go to add the pins on the metal1 layer, I can't for the life of me figure out why everything seems connected. If i delete my output metal1 between nmos and pmos, gnd and vdd separate. Why does it seem like it's "conducting" pin names through the nwell, pactive, and nactive? What am I missing? Thank you!

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Alex Soyer over 1 year ago

Hello Eth7an,

In your techfile you need to define the poly as a stop layer for the pactive and nactive otherwise the tool would consider the Drain and the Source of your transistors as connected.

Thanks,

Alex
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Alex Soyer over 1 year ago

Hello Eth7an,

In your techfile you need to define the poly as a stop layer for the pactive and nactive otherwise the tool would consider the Drain and the Source of your transistors as connected.

Thanks,

Alex
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