• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Post-layout simulation without spectre view in transistor...

Stats

  • Locked Locked
  • Replies 6
  • Subscribers 126
  • Views 5615
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Post-layout simulation without spectre view in transistor cell

Javadgo
Javadgo over 1 year ago

Hi,

I'm new to extraction and post-layout simulation. I can extract parasitics and generate "av_extracted" view. I can also do post-layout simulation using ADE-L>Setup>Environment>Switch View List and adding "av_extracted" before "spectre".

However, I want to use a config file for more control over the view for each block. The problem is, when generating the config file, I noticed that the transistors model in my PDK do not have spectre view. Using other views like "auCdl" or "auLvs" will not give me the correct answer in my post-layout simulation.

Any suggestion to solve this issue?

  • Cancel
  • Andrew Beckett
    Andrew Beckett over 1 year ago

    How did you run pre-layout simulation?

    You might want to contact the foundry that provided the PDK.

    Andrew

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Javadgo
    Javadgo over 1 year ago in reply to Andrew Beckett

    Thanks Andrew,

    I just put the transistor from PDK into my testbench, and the simulation is running smoothly!
    Is there a way for me to examine in detailed how the spectre is using these transistors in my pre-layout simulation, perhaps through a netlist or similar means?

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Andrew Beckett
    Andrew Beckett over 1 year ago in reply to Javadgo

    Which transistor? Are you instantiating lvtnfet or lvtnfet_b? Maybe there's a difference. I don't know enough of the details of this specific technology - so that's why contacting the foundry makes sense.

    Andrew

    • Cancel
    • Vote Up +1 Vote Down
    • Cancel
  • Javadgo
    Javadgo over 1 year ago in reply to Andrew Beckett

    Got it, Andrew. I'll reach out to the foundry. Thanks!

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Frank Wiedmann
    Frank Wiedmann over 1 year ago in reply to Javadgo

    I happen to be familiar with this type of PDK. You should probably make sure that you are using the templates from the PDK for your configs. As a workaround, you might also add SimMosfetAccurate to both the View List and the Stop List.

    • Cancel
    • Vote Up +1 Vote Down
    • Cancel
  • Javadgo
    Javadgo over 1 year ago in reply to Frank Wiedmann

    Thank you, Frank! Your suggestion to add SimMosfetAccurate to both the View List and Stop List worked perfectly for me. Now I can see the post-layout result. I'll also reach out to the foundry to inquire about the official template, if there is any.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information