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Negative time step with ADE_L transient simulation

ccsim

I have an application that is calling external c-code in using verilog-A for a transient circuit simulation. The c-code saves a log file that reports the time steps the simulation sent it, and I've noticed that sometimes the time-steps are negative.

The c-code is tracking the state of a circuit between function calls. I need to know the correct behavior to take when Cadence asks for a negative time step.

Should I run the system backwards in time? i.e. if I have a resistor in series with a capacitor in my c-code, and the resistor is biased so that current flows through the resistor and onto the capacitor, should I remove charge from the cap during a negative time step? Or should I ignore that time step and keep the initial state of my circuit?

What is the solver doing that it needs to take negative time steps, and are they avoidable? 

Thanks!

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