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MOSFET dimension in schematic and LVS mismatch in TSMC 180nm I/O library

JadeCircuit

I am using an analog I/O pad library from TSMC180nm. The schematic view is imported from a Spice file. The layout is from a GDS file. 

I attached an example of a pmos showing this issue. In the schematic view, the l and w are set to 0.4u and 54u to match the dimensions in the layout. However, the dimensions become other numbers when running LVS therefore giving LVS errors. 

If I change the dimensions in the schematic, the numbers shown in LVS will also change, but they never match the numbers in the schematic.

Any help is appreciated!

 

  • Looks like the schematic netlist might be in error.

      Check the netlist. What values are present? Are parallel devices merged?

      Check CDF for auCdl netlisting. W/L might not netlist the values as you see on the form.

      Why not LVS against the source spice?

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