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how to export clock crossing to file

Karev11

Hi,

in our simulation, we need to capture clock frequency changes which is very slowly and if we finish the transient sim and apply "frequency" function, it will require large disk even w. limited saved nets.

one work around can be chop the simulation to smaller runs and piece them together but that is tedious.

I wonder if there is any Verilog-A example code that could check crossing point of defined threshold and export that time point continuously to a file?

thanks!

Kevin

  • I'd be surprised that saving a single signal would really be significantly better than writing out an ASCII file with just the time info of the crossing, but you could use the freq_meter component from ahdlLib for this. Add:

    DEFINE ahdlLib $(inst_root_with:tools/dfII/bin/virtuoso)/tools/dfII/samples/artist/ahdlLib

    to your cds.lib to access this library.

    Andrew

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