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Netlist error

Greetings,

I'm a phd student in the rf design field. Usually (in my master formation at least) I used to work with cadence already installed and everything working perfectly from the beginning.

However in the lab I'm working in I had to work with the it engineer to install everything from scratch.

the technology that we're working with is a new one Bicmos 55nm from Stmicroelectronics.

Currently I'm trying to simulate a schematic circuit in maestro and I have a netlist error. This is frustrating as it seems that I can't resolve this issue.

Begin Incremental Netlisting Apr 12 16:55:04 2024
ERROR (OSSHNL-116): Cannot descend into any of the views defined in the view list 'spectre cmos_sch cmos.sch schematic veriloga' specified
for library 'cmos065_rf' and cell 'npnxhs' for the instance 'Q0' in cell 'PA_cmos/inv/schematic'. Add
one of these views or modify the view list so that it contains an existing
view.

This is the error that I'm getting

Parents

Andrew Beckett over 1 year ago

If you look in the library manager at cmos065_rf/npnxhs what views does it have?

Andrew
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BARID over 1 year ago in reply to Andrew Beckett

Hello Andrew,

Thank you for your quick reply ! Right now it's the week-end break and I can't access the lab so I'm gonna look again on monday but from what I remember it was "symbol layout " and some other cells I don't remember very well I think it was auLvs auCdl and SimBipHicumL2. I remember for sure it didn't have the spectre view. Do you think that's the cause ? Because some collegues in grenoble (south of france) that are working on the same project and they have the same npnxhs that we have and they can simulate it on maestro just fine.
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Andrew Beckett over 1 year ago in reply to BARID

If it really only has those three views, then yes, that would explain it. I'm not familiar with the particular requirements of this PDK - but maybe you just need to put SimBipHicumL2 in the view list (Setup→Environment)? I'd expect anything special like this to be documented as part of the PDK.

Andrew
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BARID over 1 year ago in reply to Andrew Beckett

I tried this solution and when I'm doing the simulation, the bicmos transistor is treated as a open circuit, there is no collector current.

I'm trying to read the documentation of the pdk but I'm not finding anything at the moment
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Frank Wiedmann over 1 year ago in reply to BARID

Did you also put it in the Stop List (as mentioned in the link I referenced)?
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BARID over 1 year ago in reply to Frank Wiedmann

Yes If I put it in the stop list I have an error. What does it mean exactly to re-netlist all cell views where this primitive is instantiated ?
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BARID over 1 year ago in reply to Frank Wiedmann

Yes If I put it in the stop list I have an error. What does it mean exactly to re-netlist all cell views where this primitive is instantiated ?
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Children

Frank Wiedmann over 1 year ago in reply to BARID

I suggest that you contact whoever is responsible for installing the PDK and sort it out with them (showing them this error message). My guess is that you are failing to call some required initialization routines.
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Andrew Beckett over 1 year ago in reply to Frank Wiedmann

The problem is not to do with the need to re-netlist all cells. The issue is the missing netlist procedure: UartSpectreDirectSubcktCall. That suggests that something in the PDK is not set up or loaded properly - that's part of the ST PDK, I believe.

As Frank suggested, you should contact both whomever installed the PDK and ST if necessary.

Andrew
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