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probe internal bus voltages

sunil09

Hi,

I would like to probe 4sets of 8bit buses internal to a block (internal ADC outputs) from test bench level. At the test bench level, i will then be applying these bus voltages/signals to a veriloga block for further processing. Now, i am probing one internal net at a time using  a deepprobe each  by setting

heirarchical node to ADC.DIG1\<0\> on the deepprobe

May I know if there is a way to probe the whole bus at once, rather than probing one net at a time. That could be something like setting
heirarchical node to ADC.DIG1\<8\:0\>

Thank you!!

  • The deepprobe component doesn't (currently) support buses. There's an enhancement change request, CCR #1676745 which is requesting this - I see there's a proposed fix, but I don't know yet how this is intended to work.

    For now, your best bet is probably to use out-of-module references within a Verilog-A module (perhaps using a genvar to iterate over the bus to create the connections) to do this. I don't have an example to hand of doing this though...

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Thank you Andrew!! Will try that.

    +++++++++++++++++

    so this is how far i managed to get..below is the verilog a code..

    ==============================

    `include "constants.vams"
    `include "disciplines.vams"

    `define TOTAL_BITS 4

    module deepprobe_4bits(NET);
    output [`TOTAL_BITS-1:0] NET;
    electrical [`TOTAL_BITS-1:0] NET;

    parameter string hierBusNet = "testBlock.net";
    string busIter;
    string netName;
    //electrical netName;

    analog begin
    generate i (0, `TOTAL_BITS-1) begin
    $swrite(busIter,"\\<%d\\>",i);
    netName = {hierBusNet, busIter};
    $strobe(netName);
    V(NET[i]) <+ V(netName);
    end

    end// analog

    endmodule

    ========================

    When i run this code, I get an error saying "no discipline was specified for `netName'." - this is for the line highligted in yellow.

    Now,  if i include the line commented out (highlighted in grey), i get  "Attempting to redefine identifier 'netName'. Remove the extra definition or use a different identifier"

    if i remove string netName, i get "Encountered invalid type conversion for `netName' (`string' to `node')"

    Not sure how to convert  from string to electrical, i think this is what i am missing.

    Thank you!!

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