automating schematic to post layout simulation flow

Basically, I want to know how to call the auto placer and auto router from the command line. 

Basically, I want to know how to call the auto placer and auto router from the command line. 

Please see...

Virtuoso Layout Suite SKILL Reference (cadence.com)

Specifically Virtuoso Layout Suite SKILL Reference -- vcpfeRunCustomDigitalPlacer (cadence.com)

... and associated functions.

Virtuoso Layout Suite SKILL Reference -- Space-based Router Functions (cadence.com)

Thank you. So far, I have successfully executed the following 3 steps using the SKILL code. 

1. Generate from schematic

2. modgen creation (my old post helped a lot, https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/38265/skill-command-for-layout-execution)

3. automatic placement

for routing, I am calling the following function 

rteOptimizeRoute(
?cv (geGetEditCellView)
?critic t
;?checkAntenna t
;?detailCritic t
;?excludeNet ""
;?excludePowerGround ""
?reduceVias t
;?region ""
;?set t
;?useDoubleCutVias t
)

But it does not seem to be routing anything.

****************************************************************************
INFO: Router used all 32 hierarchy levels for loading the layout data.
****************************************************************************
=== interpreted: -check_rule { minarea minedge minenclosedarea minwidth samenet samenet_crossing }
Begin droute...
Begin clean...
### attempted 0; success 0; guides 0;
End clean 0.0s (kernel), 0.0s (user), 0.0s (elapsed), 2294.0MB vm, 2294.0MB peak vm
Begin critic...
End critic 0.0s (kernel), 0.0s (user), 0.0s (elapsed), 2294.0MB vm, 2294.0MB peak vm
End droute 0.0s (kernel), 0.0s (user), 0.0s (elapsed), 2294.0MB vm, 2294.0MB peak vm
Begin critic...
0 routes were changed.
End critic 0.0s (kernel), 0.0s (user), 0.0s (elapsed), 2294.0MB vm, 2294.0MB peak vm

Am I missing something?

Thanks. Is this the function to use for routing the nets?

rteOptimizeRoute()

It does not seem to be routing anything.

After the routing, I also need to create labels for the pins; otherwise there is LVS mismatch. Could you also share how to automate the label creation process? 

I have had some success in automating the flow, but I need help to move further. Here are the details of what I have done so far and what is missing. I am sharing this through a Google Drive link as I have been unable to post the content here. 

https://docs.google.com/document/d/1qRC95SYJFRmwyvdZ9grFzQ8W-OvS8G0U/edit?usp=share_link&ouid=101268368332665463426&rtpof=true&sd=true

I am also trying to reach Cadence online support through a university representative. 

Any help is highly appreciated. 

Regards

Supriyo

If you get the cellview data object for the layout, you can iterate through the terminals, pins, and figures to add a label at the center box of terminal pin figure.

Routing is tough. I see you're using IC6.1.8. There's a number of ways to route, I'll mention a couple here:

1. you can use the Wire Assistant to create a routing preset. Then call the preset like this:

   vsrLoadPreset("myPresetName")
   _iaAutomaticExecuteCmd('autoRoute 'all nil)

You can also do 'selected instead of 'all.

2. The more complex way, find the Cadence Space Based User Guide, and the Command Reference. You'll write a routing script in TCL syntax and call it in SKILL with:

rdeSource("/path/to/my/tcl.script" t t)

Unfortuantely, you really need to understand the concepts of constraints, constraint groups, and constraint precedence to even become functional with this approach. It's very powerful but very tough to use and harder to debug.

Thanks a lot. I am trying solution 1 now, which gives better results than lxSelectedRoute. However, I still have to keep the GXL editor open for Solution 1 to work. Otherwise, I get the following error, although the preset file exists in the dir. 

*Error* (IA-30123): Unable to load preset file autoDeviceRouting.preset from directory /home/local/eda11/sm84275/workspace/****/.cadence/dfII/ia/presets.

                    This is because directory /home/local/eda11/sm84275/workspace/****/.cadence/dfII/ia/presets does not exist.

                    Ensure that the specified directory is exist.

There seems to be some issue with the nclAnalogAutoPlaceCB(layout_view 3) function. If I call this (load "") after step 1 from within the same file, placement looks different (right figure) than if I execute it directly from CIW (left figure). The left figure result looks correct to me as all components are contained within the PR boundary. It seems that modgen creation in step 1 is affecting nclAnalogAutoPlaceCB’s behavior. 

Please help. 

I was able to get around the nclAnalogAutoPlaceCB issue. Basically, I deleted the old PR boundary, created a larger boundary and set the lower left corner to (0,0), moved the cells inside the boundary, and then did nclAnalogAutoPlaceCB a couple of times. 

I have updated step 2 in Google Docs for reference. 

I now have an automated flow that can run from schematic to PEX. Thanks for help. 

I am having some problems running the ocean script inside CIW but I am working on it.