Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 4052
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

PCells not found for layout in Cadence Virtuoso using GF 12nm PDK

Saumeek

Our goal is to design the buffer layout using Cadence virtuoso IC23.1-64b.ISR6.30 and GF 12nm PDK. We couldn't find the PCells for the layout. Is it because the PCells are missing in the Global Foundries PDK or we haven't enabled it? If we haven't enabled, please guide how to enable it.

While using global_foundries 12LP pdk v1.0_7.0b for layout in Virtuoso Studio Layout Suite XL for our Buffer schematic, on running 'Generate all from source' in the layout tool, we have the following log:

(DEBASE-100014): VLS-EXL is not enabled.
Loading schMap.cxt
INFO (LX-1063): Building the layout generation form...
*WARNING* (DB-270001): Pcell evaluation for GFnewPDK/nfet/layout has the following error(s):
*WARNING* (DB-270002): ("dbCreateRect" 0 t nil ("*Error* dbCreateRect: Invalid layer/purpose" ("PC" "drawing")))
*WARNING* (DB-270003): Error kept in "errorDesc" property of the label "pcellEvalFailed" on layer/purpose "marker/error" in the submaster.
*WARNING* (BND-2054): The 'permuteRule' property on cellview 'GFnewPDK/nfet/layout' was ignored because it contains invalid terminal names, '(p s d)'.
In the 'Simulation Information' tab of the 'Edit CDF' form for the auLvs simulator,
set the permute rule for the cell using valid terminal names.
*WARNING* (DB-270001): Pcell evaluation for GFnewPDK/pfet/layout has the following error(s):
*WARNING* (DB-270002): ("dbCreateRect" 0 t nil ("*Error* dbCreateRect: Invalid layer/purpose" ("PC" "drawing")))
*WARNING* (DB-270003): Error kept in "errorDesc" property of the label "pcellEvalFailed" on layer/purpose "marker/error" in the submaster.
*WARNING* (BND-2054): The 'permuteRule' property on cellview 'GFnewPDK/pfet/layout' was ignored because it contains invalid terminal names, '(p s d)'.
In the 'Simulation Information' tab of the 'Edit CDF' form for the auLvs simulator,
set the permute rule for the cell using valid terminal names.
*WARNING* (LX-2003): Cannot create instance terminal on layout instance 'N0' because the instance master 'GFnewPDK/nfet/layout' does not have a corresponding terminal 'd'.
*WARNING* (LX-2003): Cannot create instance terminal on layout instance 'N0' because the instance master 'GFnewPDK/nfet/layout' does not have a corresponding terminal 's'.
*WARNING* (LX-2003): Cannot create instance terminal on layout instance 'N1' because the instance master 'GFnewPDK/nfet/layout' does not have a corresponding terminal 'd'.
*WARNING* (LX-2003): Cannot create instance terminal on layout instance 'N1' because the instance master 'GFnewPDK/nfet/layout' does not have a corresponding terminal 's'.
*WARNING* (LX-2003): Cannot create instance terminal on layout instance 'P0' because the instance master 'GFnewPDK/pfet/layout' does not have a corresponding terminal 'd'.
*WARNING* (LX-2003): Cannot create instance terminal on layout instance 'P0' because the instance master 'GFnewPDK/pfet/layout' does not have a corresponding terminal 's'.
*WARNING* (LX-2003): Cannot create instance terminal on layout instance 'P1' because the instance master 'GFnewPDK/pfet/layout' does not have a corresponding terminal 'd'.
*WARNING* (LX-2003): Cannot create instance terminal on layout instance 'P1' because the instance master 'GFnewPDK/pfet/layout' does not have a corresponding terminal 's'.
*WARNING* (LX-2006): There were errors or warnings during layout generation.
INFO (LX-1030): Run Connectivity - Check - Against Source for more details.
INFO (LCE-1007): The cell verifier found
INFO (LCE-1008): 3 open(s)
*WARNING* (BND-2054): The 'permuteRule' property on cellview 'GFnewPDK/nfet/layout' was ignored because it contains invalid terminal names, '(p s d)'.
In the 'Simulation Information' tab of the 'Edit CDF' form for the auLvs simulator,
set the permute rule for the cell using valid terminal names.
*WARNING* (BND-2054): The 'permuteRule' property on cellview 'GFnewPDK/pfet/layout' was ignored because it contains invalid terminal names, '(p s d)'.
In the 'Simulation Information' tab of the 'Edit CDF' form for the auLvs simulator,
set the permute rule for the cell using valid terminal names.

*** Checking layout cellview 'testCkt/Buffer_newPDK/layout' against source cellview 'testCkt/Buffer_newPDK/schematic'. - Tue May 28 23:57:21 2024 ***

INFO (LX-1013): Instance terminal 'd' is missing from layout instance 'N0'.
INFO (LX-1013): Instance terminal 'd' is missing from layout instance 'N1'.
INFO (LX-1013): Instance terminal 'd' is missing from layout instance 'P0'.
INFO (LX-1013): Instance terminal 'd' is missing from layout instance 'P1'.
INFO (LX-1013): Instance terminal 's' is missing from layout instance 'N0'.
INFO (LX-1013): Instance terminal 's' is missing from layout instance 'N1'.
INFO (LX-1013): Instance terminal 's' is missing from layout instance 'P0'.
INFO (LX-1013): Instance terminal 's' is missing from layout instance 'P1'.

INFO (LX-1108): Names match.

INFO (LX-1111): Schematic and layout dummy instances match.

INFO (LX-1043): Design Intent match.

INFO (LX-1024): Instance parameters match.

INFO (LX-1083): Implicit bus terminals match.

INFO (LX-1032): There are differences between the layout and the schematic.
Check messages above for details.

*** Check Against Source complete. ***

The output is that we couldn't get the instances placed and the the only one placed is PC, the other one being the marker error. Is it because the PCells are missing in the Global Foundries PDK or we haven't enabled it? If we haven't enabled, please guide how to enable it.

  • I've no idea what you've done, but the fact that the library is called GFnewPDK suggests that you have installed it in a non-standard way and maybe that's what's breaking things.

    I followed the following simple steps and everything worked:

    1. Ran the GF installer "./install-12LP-V1.0_7.0b_cadence config" and answered the questions.
    2. Set these environment variables (of course, the root location would be where it makes sense for you, and pick the appropriate metal stack - you can see the choices in $GF_PDK_HOME/DesignEnv/VirtuosoOA/setup )
      setenv GF_ROOT /external/kits/GF_PDK
      setenv GF_PDK_HOME $GF_ROOT/12LP/V1.0_7.0b
      setenv BEOL_STACK 13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB
    3. Copied the sample cds.lib : cp $GF_PDK_HOME/DesignEnv/VirtuosoOA/setup/sample.cds.lib cds.lib
    4. Edited the cds.lib to uncomment the INCLUDE line at the end which use ${BEOL_STACK}
    5. Copied the sample .cdsinit file: cp $GF_PDK_HOME/DesignEnv/VirtuosoOA/setup/pdk.cdsinit .cdsinit
    6. Ran Virtuoso (either ICADVM20.1 or IC23.1)
    7. Created a new library, and attached the technology to cmos14lpp
    8. In the new library create a new cellView and create an instance of cmos14lpp/nfet - all works OK

    If you have problems, raise a ticket with Global Foundries support...

    Regards,

    Andrew

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.