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BEOL_STACK choice visible for Pegasus LVS run, but not DRC

While running Pegasus for DRC and LVS checks on Cadence Virtuoso for our buffer schematic, I have used 7M_3Mx_2Cx_1Gx_1Ox_LB stack of GF 12nm PDK for layout:

DRC file drc.pvs.cfg does not have 7M_3Mx_2Cx_1Gx_1Ox_LB layer, But lvs.pvs.cfg has. Also, there are other stack choices in lvs file but not in drc file

So while Running LVS that option shows up in BEOL_STACK as below, but does not show up in DRC.

Please guide me.

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