How to decrease the capacitance of charging and discharging at the MSB of current steering DAC

Dear Sir
I'm designin a 3 bit binary differential current steering DAC using transmission gate as a switch in the top and the bottom of my circuit. When the transition at MSB is occured, the time of charging and discharging the capacitance is increased which make the transition more slow, as can be seen in figure below: when the binary switch from '001' to '110', the rised slope and decreased slope are not identical. It is necessary that the descent slope and the rise slope should be equal. This provide an asymmetry of the curve and i can’t reconstrut my input signal which is a sinusoidal signal. Moreover, each transition where all the bits change, the rised slope and the decreased slope i are not equal.
Also, i try to switch from "010" to "011", i have the same results. during the descent or rise of the signal, there is a change in the slope, the variation is more slower; as presented in this figure : the best case dy1 and dy2 should be equal because thay have the absolute value of slope and this is not the case. How can i decrease the capacitance of charging and discharging at the MSB of current steering DAC nad make the transition at MSB more faster. I'm so gratefull if you can help me