Switching from voltage source to high impedance port in VerilogA: Convergence problem

For my VerilogA testbench, I need a port that can act as both a voltage source, and as a high impedance.
As far as I know, there are two ways to implement a high impedance, either by assigning a 0 (or very close to 0) current to the port, or using a very high resistor value. (ex: V(port,n)<+I(port,n)*R_big  ).

Given that there is no way to use a transition while switching between current and voltage source, I went for the second way.
The problem is that when switching from a current source to high impedance, I have convergence issues. My code looks something like this:



if(write=0) begin
temp=I(port,n)*R_big;
end

else begin
temp=A_Value;
end

V(port,n)<+transition(temp,0,1n);

For more context, my ultimate goal is to be able to both charge a capacitor and sense it's voltage, through a transmission gate.
Trying the same approach with different simpler circuits, and it doesn't seem to give a problem.
I tried adding resistors to help in converging, doesn't seem to help much.

Any help would be appreciated.
Thank you.