BlackBox with Assura LVS

Hello,

I'm working on the design of a pad ring and the I/O cells have only the abstract view, with no schematic, so I am trying to do a blackbox LVS with Assura (4.1_USR6_EHF13). I am using DFII.

I created an empty schematic with just the pins (same pins as the abstract) and generated the corresponding symbol.

I followed the "Assura LVS Black Box Flow" Application Note and I added the pinLayer definitions in the extraction rules file, before setting the ?blackBoxCell command in the avParameter. I created a text file which contains all the cells that I'd like to black box and launched the LVS.

I get the following warnings from the .erc file (just one as example, but I get the same for each black box cell):

*WARNING* blackBox - cell 'PDDW0204SCDG abstract tpd018nv_MT2' does not bind to anything 

*WARNING* 'PDDW0204SCDG abstract tpd018nv_MT2' is marked as a BlackBox cell only in the layout side

If I look at the LVS error report, I get something like this. The Layout connection is fine (the signal connects to the I/O cell and to a digital buffer, so 1 NMOS and 1 PMOS gate. The connection seems to be lost in the schematic.

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 3)
Schematic Net: nRST
S 1 of nmos2v G
S 1 of pmos2v G

Layout Net: avC47
L 1 of N G
L 1 of P G
L *1 of PDDW0204SCDG ?{DS I IE OEN PE C PAD}

Am I doing anything wrong? Did I miss anything from the App note?

EDIT: I also found a solution related to that warning Warning - ... marked as a BlackBox cell only in the layout side. (cadence.com) and I tried that, but now the LVS ends with some errors such as:

*ERROR* There are two or more descriptions of the device with identical type('Generic') and name('subcircuit');
however number of terminals are not the same, details are given below.
'PDB1AC auLvs tpa018nv_MT2' pin names: [ AIO ] dfII terminal names: [ AIO ]
'PDDW0204SCDG auLvs tpd018nv_MT2' pin names: [ C ] dfII terminal names: [ C ]

Thanks,

Stefano