top level parameter transfer to lower level verilog-A block

**EDIT**

I somehow managed to succeed by changing the properties of the field in CDF editor and "forcing' to parse as CEL.

It was an intuition-based move, I don't actually know why this work exactly, so I'm leaving the topic for someone knowledgeable to help in case

I will also study a bit...

Hi,

I have following general setup/issue. My hierarchy contains a
 number of "wrapper" cells consisting of a digital controller and an analog
 controlled part. Like a DAC with its control word, for instance.

In simulation these cells - which share the same name (I mean,
 they are the *same* cell in the end) - should receive
 *different* control words, and that is where my problems start.

A first issue is that one cannot specify different /views/ for
 the same cell in a hierarchy via config, so creating a copy of the view and
 modifying its control word is no use.
The digital control part has a simple verilog-A view that I use to
 read the control word from a file and output it as voltages on a
bus. I originally thought I could simply use a parameter declaration, like:

parameter filename = "/my/path/to/file";

and change it but (of course?) this doesn't work because "a cell
 is a cell" and it is defined as a subcircuit only once, so no
luck there either.

However, when thinking about the issue from an abstract point of
 view, it occurred to me that most primitives and PDK elements we
 use all the time have in fact the characteristics I am looking
 for: transistors, capacitors, diodes, you name it, are all the
 /same/ cell with different parameters. So, if the file to read
data from is a parameter, why can't it change between instances?

And indeed placing my digital verilog-A models on *top* of a
schematic, I can freely choose to assign the data source, no problem.

I therefore need to find a way to introduce this data source as a
 parameter for the /containing/ cell, the one that wraps together
the  digital and the analog part.

I believe pPar() is what I am looking for, however while I can
 make it work seamlessly for "common" cells, I cannot make it
 work tor the verilog-A models of my digital control.

Is it a limitation of the syntax or am I just not doing things correctly?

I mean, that parameter declared above becomes a field with a
default name in the properties window of any instance of this
 digital part. So far, so good.

I can then write "pPar("file")" (without the outer quotes) in
 that field but this declaration is not recognized at the top
 level, so that my wrapper cell (containing digital and analog)
does not have a parameter "file" showing up in its properties window.

I think this has to do with the fact that I can't leave a
 parameter declaration unassigned and the moment I write
 something like "my-file" in quotes, it is interpreted as a
 string and the pPar() statement is also interpreted as a pure
string and therefore its function is completely ignored.

I tried adding the field from the CDF editor but even if the
 field now appears in the properties window, the netlist shows no
 presence of it and therefore there's no notion of transferring
the parameter value.

Is what I am trying to do at all possible? Provided I was able to
 explain my issue, if you have alternative proposal I'd be really
glad to hear from you :)

Thanks,
Michele