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Need help in extracting a SPICE from a layout

gaddan14

Hello 

I have a layout generated in Virtuoso for a simple ALU circuit. The layout was generated from a verilog code compiled by design_vision, with a floor plan and P&R created in INNVOUS and then imported in Virtuoso.
The design passed the DRC in Virtuoso in generic PDK 45.
Now I want to do the parasitic extraction for the layout and generate a SPICE netlist for the extracted version. 
The problem I am currently facing is, since I only have a layout view of the ALU and not the schematic, I am unable to run the LVS test and subsequently do the parasitic extraction for netlist generation. 
I used to extract parasitics and do the LVS for simple cells. This situation is new to me.
I thereby wanted to know if there are any procedure where I can directly extract a SPICE netlist from the layoutt?
Your help and guidance in this matter, as to what tools and processes I need to use, will be greatly appreciated.

  • You can use a Verilog top level netlist for PVS/Pegasus LVS.

    I assume it's a small digital design if intending to target a spice netlist. What simulator are you intending to use?

    Consider dspf or new i-dspf flow instead of spice.

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