Stats

  • Locked Locked
  • Replies 3
  • Subscribers 125
  • Views 3715
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

An instance parameter cannot be a variable when using the SFE parser

MikeA

Hi,

I am adding some Spectre primitives to my Verilog-A model and just found these can't contain variables as values, just checking whether there is a way to overcome this limitation and, in case, for an explanation of the root cause.

My module has something like:

module my_module(a,b)

...

real mynumber = 3;

cap #(.c(mynumber)) c_test  (a,b);

And parsing gives the error in the title. There's no such error if I define `mynumber` as a parameter, but then I have it appearing in the properties dialog and this is something I don't necessarily want to have since the number of these variable parts might start to grow.

Thanks for any hints you might like to give Slight smile

Michele

  • Andrew Beckett

    No, this is not supported. If you had:

    parameter real mynumber=3;

    then it would be OK - and you can override mynumber on the instance of my_module too - because then it's constant. This is documented in the Verilog-A documentation:

    Overriding Parameter Values from the Module Instance Statement
    Using the module instance statement, you can assign values to parameters by explicitly
    referring to parameter names. The new values must be constant expressions. The format for
    overriding a parameter value on an instance statement is as follows:
    moduleName # (.parameterName(constantExpression)) instanceName (ports) ;
    For example:
    vdoubler # (.parm3(4.0)) vd1 (qin, aa1) ;

    The challenge if it was a variable is that the component value would change over time and this is something you can't do in spectre either (other than via dynamic parameters in transient, which allows changing at discrete times rather than in the solver loop). Changing over time could lead to topology changes and would also be difficult for the convergence algorithms too.

    Andrew

  • MikeA
    in reply to Andrew Beckett

    Thanks for the quick reply Andrew!

    I didn't think of the fact that other variables not defined as parameters could in principle change during simulation, now that you say that, it's pretty clear!

    BTW, can you point me to the exact name of the documentation for Verilog-A in the Virtuoso Help? Or any other place in the support portal?

    I see the AMS manual and I know Verilog-A is a subset of -AMS but I can't see a verilog-A language reference manual in the docs.

    (There is some sort of appendix in the "other simulation topics" of the Spectre Reference, but not a "complete" manual)

    Regards,

    Michele

  • Andrew Beckett
    in reply to MikeA

    Hi Michele,

    The manual is in the Spectre installation (so you can access with "cda" or "cdnshelp" run from the SPECTRE stream, or by pointing to the documentation library there). It's called <SPECTREinstDir>/doc/veriaref/veriaref.pdf and is also here: Cadence Verilog-A Language Reference

    Regards,

    Andrew

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.