Stats

  • Locked Locked
  • Replies 1
  • Subscribers 129
  • Views 3631
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Weird negative voltage dip when charging capacitor to high voltage via a PMOS

Yaohua2024

Hi guys,

I have encountered a really strange problem and I cannot figure out the reason behind it. I have a simple circuit to charge up an RC network to VDD via a PMOS (see schematic attached). This is a regular 3.3 V PMOS in a bulk 180 nm CMOS technology. The source of this PMOS is connected to a dc voltage of 3.3 V (vdc in analoglib). The bulk is shorted to its source, whereas its drain is connected to the RC (R is 1000 ohms, C is 137 pF with initial condition set to 0). Its gate is connected to a control signal (vpulse in analoglib). This control signal starts at 3.3 V and drops to 0 V after a delay of 800 ns. The details of this vpulse control are shown in the screenshot below. 

When this PMOS is enabled, we expect its drain voltage to start to increase from zero to VDD. However, the strange thing is that its drain voltage dips to a negative voltage for a short period of time before increasing up to VDD. The zoomed in view of this negative dip is attached as a screenshot below. This negative voltage excursion also varies with other factors such as the size of R, and the rise/fall times of the control signal. 

Can anyone explain why such a negative voltage dip happens? I am baffled by this as it does not make any sense to me.

Any help would be greatly appreciated, especially with such a problem that seems to defy common expectations!

Thanks,

YH

  • Yaohua2024

    Hi, I thought about this over the weekend and I believe I have figured it out. I was naive in my previous reasoning because I forgot about the parasitic CGD. CGD was originally charged to VDD, and when the gate voltage starts to decrease, CGD will try to maintain its original voltage by pulling the drain node negative. Eventually, when the PMOS is fully turned on, the drain node will be pulled up. Hope this helps anyone who has the same confusion as me!

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.