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  3. Transient simulation missed important points.

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Transient simulation missed important points.

JeyJey
JeyJey over 1 year ago

Hi.
I wrote VerilogA ideal switch (V(in) <+ V(out) which has parameter delay (when to turn on the switch).

When I toggle the switch the input signal is stabilized and pretty constant, and the simulation starts to sample the signal with big time intervals.
In the VerilogA cell I define , for example : close after 200us for 1us.

In simulation around 200us the simulation performs intervals ~2us and it misses the switch operation at all.

How can I fix it without to limit maximum time step for entire simulation ?

I don't know much about Verilog-A, so if this is solved in code, give me an example, please.

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  • Andrew Beckett
    Andrew Beckett over 1 year ago

    Rather than guessing what you've done, please share the Verilog-A model. That way we can see what you might have done wrong (my guess is that there's no real event to change the switch; limiting the timestep is almost certainly the wrong way to solve this).

    Regards,

    Andrew

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  • JeyJey
    JeyJey over 1 year ago in reply to Andrew Beckett

    `include "constants.vams"
    `include "disciplines.vams"

    module delay_duration_component(in, out);
    input in;
    output out;
    electrical in, out;
    parameter real Delay = 1u from (0:inf);
    parameter real Duration = 10n from (0:inf);
    real t_start, t_end;

    analog begin
    @(initial_step) begin
    t_start = $abstime + Delay;
    t_end = t_start + Duration;
    end

    if ($abstime < t_start) begin
    V(out) <+ 0;
    end else if ($abstime < t_end) begin
    V(out) <+ V(in);
    end else begin
    V(out) <+ 0;
    end
    end
    endmodule

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  • Andrew Beckett
    Andrew Beckett over 1 year ago in reply to JeyJey

    You need to use the timer event to ensure there is a time step at the switch transition. Here's a way of rewriting your model (with some suggestions as to other places to look in the comments):

    `include "constants.vams"
    `include "disciplines.vams"
    
    module delay_duration_component(in, out);
    input in;
    output out;
    electrical in, out;
    parameter real Delay = 1u from (0:inf);
    parameter real Duration = 10n from (0:inf);
    real t_start, t_end;
    integer switch_pos;
    
    analog begin
      @(initial_step) begin
        // note, if the transient simulation has start=0.2u (say), then
        // this means that the switch start will be delayed too. Is that
        // what you want?
        t_start = $abstime + Delay;
        t_end = t_start + Duration;
        switch_pos = 0;
      end
    
      // timers ensure there is a timestep at the switch change
      // time
      @(timer(t_start)) switch_pos = 1;
      @(timer(t_end)) switch_pos = 0;
    
      // use a switch branch - this changes from a voltage to a current
      // might want to use some non-ideal switches. See relay models
      // at designers-guide.org/.../index.html for ideas
      if (switch_pos>0)
        V(out,in) <+ 0;
      else
        I(out,in) <+ 0;
    
    end
    
    endmodule
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  • JeyJey
    JeyJey over 1 year ago in reply to Andrew Beckett

    Thank you very much.

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  • JeyJey
    JeyJey over 1 year ago in reply to Andrew Beckett

    Can I add between  V(out,in) <+ 0 and  I(out,in) <+ 0 rise and fall time ?
    I didn't find similar in your link with models.

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  • Andrew Beckett
    Andrew Beckett over 1 year ago in reply to JeyJey

    No, you can't do that with a switch branch.

    You could use it with some kind of multiplexer such as the "multiplexer" in ahdlLib. This isn't quite the same as it ends up being a voltage-controlled-voltage source (rather than an actual connected switch as the example I gave above) but you could use something like this to switch between the input voltage and 0V at the time you want, and use the slew() function to manage the transition (probably should give the second argument to slew to specify the rate - the example in ahdlLib doesn't have this).

    Andrew

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