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Generating input of schematic in cadence virtuoso using verilog.

AK202409055824

Dear All , 

 i am designing the schematic in cadence virtuoso after that at the point of applying inputs to the schematic, i am using vsource and other input sources. however i want to gennerate the schematic input (say input of inverter) using verilog in cadence for that i would like to ask how can i apply input to any schematic in cadence virtuoso using verilog.

Thank you.

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