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Simulating Verilog Code with AMS simulator

Doronzzz

I've created a functional view and wrote a counter as follows:

module counter (
out,
enable,
clk,
reset
);

//----------Output Ports--------------
output [7:0] out;
//------------Input Ports--------------
input enable, clk, reset;
//------------Internal Variables--------
reg [7:0] out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out + 1;
end


endmodule

Then I put the symbol of this counter into a schematic and connected it to some voltage sources. I did a test and found that the verilog module treated voltage above 1.2V as logic one. So I applied 1.5V pulses to clk, and got something as shown below: the counter added 2 when a rising edge arrived, but when I made the rising sharper, it worked fine.

My questions are: 1) Is the simulation correct and does it mean that the counter may fail when the transition is not sharp enough?  2) Why is the threshold about 1.2V, is it defined by PDK?

  • These thresholds, as well as voltage values for digital high and low (vh, vl) are defined by connect modules that you need to set up for mixed-signal simulation.

    This article is probably a good starting point: FAQ: Frequently Asked Questions related to connect modules (CMs) / interface elements (IEs)

  • in reply to Alonso Schmidt

    Thanks for your reply! It works well when I changed the tr to 100n in the IE Card Setup, but I'm still confused what does the tr mean? Why the counter adds by 2 when tr is set 0.2n in the IE Card Setup (while the clk's rising time is 100n)?

  • in reply to Doronzzz

    The reason is as follows:

    1. The threshold for a low output (vtlo) is 1/3 of the supply
    2. The threshold for a high output (vthi) is 2/3 of the supply
    3. If a signal is between the low and high thresholds for longer than txdel (which defaults to 4*tr) then it will become unknown (X).
    4. So what happens is that because it takes a significantly long time on the rising edge compared to tr, the clk at the output of the connect module goes from 0 to X and then to 1 when the high threshold is crossed. This 0 to X causes one event in your counter, and the X to 1 causes another event - hence the double count. 

    This is only an issue because the defaults are somewhat reasonable and a rise time of 100ns is quite unusual. Either way, you should set up typical rise times and supplies for your connect modules on the IE card setup form to ensure the modelling is reasonable.

    Andrew

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