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Behavioral modeling of clock gating for efficient analog simulations (Spectre)

ItsMichael
ItsMichael 10 months ago

Hello all,

I have a question regarding the simulation of mixed-signal or clocked analog circuits in Spectre, particularly when the clock is not provided for the entire transient simulation.

My specific concern is if the clock is gated using a simple AND gate (or a behavioral AND gate), does Spectre automatically isolate the clocked (high-frequency) nodes from the rest of the circuit?
Does Spectre inherently optimize time steps such that when the clock is not enabled, only the clock nets are evaluated in small time steps while the rest of the circuit can be evaluated in much longer time steps?

If Spectre doesn't handle this optimization inherently, are there ways to improve simulation efficiency?
For instance, could using a Verilog-A based clock generator help optimize the time steps?

Any insights or experiences you can share would be greatly appreciated.

Thanks in advance,

Michael

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  • Alonso Schmidt
    Alonso Schmidt 10 months ago

    Hi Michael,

    The strategies of separating the clock from the rest of your circuit and evaluating different time step sizes in each of them are FastSPICE technologies known as partitioning and multi-rate simulation. Cadence FastSPICE simulator Spectre FX employs them, but not the pure SPICE simulators as Spectre X, APS and Classic.

    If you use an analog block (analog begin... end) inside a Verilog-A(MS), it will not help because that triggers the time-step based analog solver too. However, you should be able to improve your simulation efficiency by modelling this high-frequency part of your design in a digital context by avoiding the analog block and running an AMS simulation. If you do that, the digital simulator (Xcelium) will take care of this part with an event-based approach (triggered by clock edges and bit flips). And the analog part of your design will simulate with larger time-step sizes, except when there is a D2A (digital to analog) event at one interface element between the digital and analog parts.

    Regards,

    Alonso

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