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  3. How to Automatically Print Design Checks/Asserts in Simulation...

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How to Automatically Print Design Checks/Asserts in Simulation in Virtuoso Assembler by Default

baltaci
baltaci 10 months ago

Hello,

I am using IC23.1.

Normally, I can manually enable design checks and asserts to be printed in the simulation log by going to Options → Analog... → Check, and then selecting "both" for the checklimitfile option. However, if this is not done manually, the design checks and asserts do not appear in the simulation log.

I would like to configure Virtuoso Assembler so that design checks and asserts are always printed in the simulation log file automatically, without needing manual intervention. This setting should apply for all users and be effective whenever Cadence is launched.

Could you please guide me on how to make this the default behavior?

Thank you!

Can

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  • Andrew Beckett
    Andrew Beckett 10 months ago

    Can,

    I assume you meant checklimitdest rather than checklimitfile? Anyway, you can set that with:

    envSetVal("spectre.opts" "checklimitdest" 'string "both")

    Note this will only affect newly created tests, not existing tests (because it would not be possible to distinguish between somebody consciously setting this or picking up the old default).

    Andrew

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  • Andrew Beckett
    Andrew Beckett 10 months ago

    Can,

    I assume you meant checklimitdest rather than checklimitfile? Anyway, you can set that with:

    envSetVal("spectre.opts" "checklimitdest" 'string "both")

    Note this will only affect newly created tests, not existing tests (because it would not be possible to distinguish between somebody consciously setting this or picking up the old default).

    Andrew

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  • baltaci
    baltaci 10 months ago in reply to Andrew Beckett

    Andrew,
    You were right—I meant checklimitdest.
    I tried it, and the solution worked. Thank you very much!
    Can

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