function for thermometric code from digital bus

You can easily convert a number to the nearest thermo value, with e.g.
floor(log( <number> )/log(2))+1

This just looks at the highest bit and would thus also work for one-hot encoding. Other encodings of the bus value, e.g. gray code, could be handled similarly.
If you, however, want error handling, e.g. doing some majority decision, or just check if all bits of the thermo sequence are set with e.g. !(<number> & (<number> + 1)), it will get a bit more complicated. But for this the question is not specific enough.

For the second, to convert a digital waveform to an analog, you can use the Measurements > Digital To Analog in the ViVA menu, the corresponding skill function is awvDigital2Analog.

Regards,

Thank you!

By the way, I didn't see the original post (there's a bug in the forums at the moment where some notifications are not being sent), but I think it's not trivial to adapt the code you reference to handle thermometer encoded data (particularly with the points that henker makes about error handling).

Andrew

It might be an option to apply a separate bus conversion module e.g. in veriloga, which takes a thermo-coded bus as input and outputs the value as binary-coded bus. This can than be displayed with the existing functionality.
There is an example for the opposite conversion on edaboard (look for verilog-a-model-for-binary-to-thermometer-decoder, the external link is classified as spam), which might be a good starting point.

Regards,

I have tried using awvDigital2Analog, unfortunately such function seems to convert the bus to an analog voltage taking its value as if it were an unsigned decimal, whereas most of the times I am using signed decimals.
Is there any way to get the signed values instead?

(I could also create my own verilogA model to process the digital bus, however I am running AMS simulations and the digital bus is actually a net within a systemverilog precompiled module, therefore I am not even aware of a way to bring out to the testbench level such net and connect it as input to the aforementioned verilogA model). Besides this, I feel this should be a built-in function as it seems something of quite general utility, maybe is there already something to do this?

numConv seems to work on single numbers only, not on a waveform.

awvDigital2Analog has e.g. arguments ?mode and ?outWaveType to determine the type of the output, please look up the corresponding values in the manual that fit your requirements.

Further, the veriloga is the way to handle this completely within analog domain.
If you run an ams simulation than you have more options:

1) a verilogams module with electrical input and logic output for the thermo-to-binary translation. The logic output signal would then directly plot as digital waveform. This would remove the hassle with the extra conversion for waveform display of the output.

2) use pure digital verilog with all logic ports. The simulator will than take care of the connected signals:
- when connecting to a digital net, no signal conversion is required and everything is handled in digital domain
- when connecting to an analog net, then the simulator will automatically insert connect modules for a2d / d2a conversion on the ports of the modules. So no need for manual conversion inside, although you have less control on load, timing, thresholds, etc.
This is also how the connection of the digital signal from your current systemverilog to the veriloga would be handled.

Each option has advantages and disadvantages and you may choose depending on your requirements.

Regards,

NewScreenName said:

Besides this, I feel this should be a built-in function as it seems something of quite general utility, maybe is there already something to do this?

It does not seem to have been widely requested - I can find a single request from a number of years ago, Cadence Change Request #1174536. You could contact customer support and request a duplicate.

Since the digital thermometer encoded bus is within the SystemVerilog, you could write some Verilog or SystemVerilog code to reference that bus (via an out-of-module-reference) and convert it to a conventional signed or unsigned bus, or even just an integer or real value directly. That way you can accommodate whatever error correction scheme you wish to adopt (this is one challenge with a built-in function; how do you determine which error correction mechanism you're going to adopt - for example if you have gaps in the coding such as 1111101 for just one example; you kind of need to know how the destination for this encoded signal is going to handle invalid codes).

Andrew