Is it possible to access design variable as parameter of systemverilog bloc

Hi everyone,

I'm doing an AMS simulation in which I want to parameterise a output generated by a systemVerilog instance . This should be used in an existing AMS simulation to enter this parameter as an input bus to the DUT.

module test_parametrized_input (Out );

output logic[63:0] Out;
parameter xValue=2;
assign Out=xValue;
endmodule

Here is the maestro view with xValue declared as a design variable:

I tryed to do as in this post in which variable is declared as a parameter with the same name than the design variable.

However it does not seem to work in ams simulation system-verilog.

Hence I wonder if it is even possible ? or must I do it in verilog-a ?

Thanks in advance for your future answer.

Best regards