veriloga error between spectre and ams

Are you running from ADE? If so, this shouldn't happen unless you have checked the Comple Verilog-A as Verilog-AMS checkbox on the Simulation->Netlist and Run Options form.

The default flow is to use Verilog-A from within the Spectre engine as this is more efficient.

I see a long-standing request for ANSI support for Verilog-AMS (although at the time the LRM didn't support this for disciplines, it does now) - maybe there's a more recent request but I didn't find it. I suggest you contact customer support (submit a support case after logging in) - and an enhancement Jira can be filed on your behalf. However, I think the solution in your case would be the checkbox above.

Regards,

Andrew

Comple Verilog-A as Verilog-AMS checkbox was checked by default. Maybe the EDA team made it that way. Once I unchecked it these errors went away. But I got a strange fatal error message when the output is multibit.
Notice from spectre during initial setup.
Ignorevaref=yes is ignored since all nodes are connected to Verilog-A modules.
Fatal error found by spectre during topology check.
FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
sample_sim.I0:o_b[3]_flow (from sample_sim.I0___dUmmY_pORt_2_ to 0)
sample_sim.I0:o_b[2]_flow (from sample_sim.I0___dUmmY_pORt_2_ to 0)
sample_sim.I0:o_b[1]_flow (from sample_sim.I0___dUmmY_pORt_2_ to 0)

This error occurs only for method 1. For method 2 it doesnt occur.

xrun log says version is xrun(64): 23.09-s008

When I check help->about in ADE-L I get "Virtuoso custom IC design environment version ICADVM20.1-64b.500.34

This error indicates. you have voltage sources in parallel, or current sources in series (some other scenarios too). Without seeing the model and the context in how it's used it's hard to know the root cause or whether it's caused by some simulator optimisation. I suggest you contact customer support so that we can look at it with you.

Andrew

I am planning to anyway go ahead with 1995 style for now since cadence support also mentioned that they don't support ANSI style for AMS(since it is not part of LRM)

But putting the code and context below so that it might help someone later if there is a solution for this and Cadence decides to support ANSI style in AMS.

module sample
(
input electrical VDD,
input electrical VSS,
input electrical i_a,

output electrical [3:0] o_b

);

localparam b_val = 13;
localparam b_bits = 4;

integer compare_bit;
genvar i;

analog
begin
for(i=0; i<b_bits ; i=i+1)
begin
compare_bit = (b_val >>i)&1;
V(o_tm_amp_corr[i]) <+ compare_bit ? V(VDD) : V(VSS) ;
end

end

endmodule

Basically this block just drives bits of the output o_b to VDD(logic 1) or VSS(logic 0) based on the value b_val. In this case b_val is 13(binary 1101).

This block I create symbol view.

This symbol I am instantiating in a schematic and adding analog lib vdc(say 1.2V) and connecting +ve terminal of vdc to VDD and all other inputs to -ve terminal of vdc. Output is floating. I just simulate the schematic in adel with transcient sim say 2ns. And it gave the error mentioned in the above comment.

I also tried connecting output to basic lib noConn <3:0> still the error is same.