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VCD File Simulation using Spectre

VK202409108412

I have first imported the verilog (.v) file for a digital block into Cadence Virtuoso and created its symbol for it. 

 

Now, I have extracted the VCD file for it as shown below: 

The testbench for it shown below:

How can I use the VCD file as an input for this testbench in Spectre? The block generates two bus signals, d<3:0> and sel<1:0>, but in the VCD file, these signals are defined individually as separate bits. How can I properly simulate this setup while ensuring the bus signals are correctly interpreted?

I have loaded the VCD file in Result Browser and generated the analog signals. However how can we proceed further?

Parents Reply Children
  • in reply to Andrew Beckett

    Sure. Here is the VCD file contents: 

    $timescale
    1ps
    $end

    $scope module dff_mux $end
    $var wire 1 ! clk $end
    $var wire 1 " d[0] $end
    $var wire 1 # d[1] $end
    $var wire 1 $ d[2] $end
    $var wire 1 % d[3] $end
    $var wire 1 & reset $end
    $var wire 1 ' sel[0] $end
    $var wire 1 ( sel[1] $end
    $upscope $end
    $enddefinitions $end
    #0
    $dumpvars
    0!
    0"
    0#
    0$
    0%
    1&
    0'
    0(
    $end
    #5000
    1!
    #10000
    0!
    0&
    #15000
    1!
    #20000
    0!
    1%
    1#
    #25000
    1!
    #30000
    0!
    #35000
    1!
    #40000
    0!
    1'
    #45000
    1!
    #50000
    0!
    #55000
    1!
    #60000
    0!
    0'
    1(
    #65000
    1!
    #70000
    0!
    1'
    #75000
    1!
    #80000
    0!
    0#
    1$
    #85000
    1!
    #90000
    0!
    0'
    0(
    #95000
    1!
    #100000
    0!
    1'
    #105000
    1!
    #110000
    0!
    0'
    1(
    #115000
    1!
    #120000
    0!
    1'
    #125000
    1!
    #130000
    0!
    #135000
    1!
    #140000
    0!
    0'
    0(
    #145000
    1!
    #150000
    0!
    1'
    #155000
    1!
    #160000
    0!
    0'
    1(
    #165000
    1!
    #170000
    0!
    1'
    #175000
    1!
    #180000
    0!
    #185000
    1!
    #190000

  • in reply to Andrew Beckett

    Sir, I have uploaded the VCD file and the .info file in ADE-L → Setup → Simulation Files → Vector Files. The transient simulation is running successfully, but there is an issue with the bus signals(d[3:0] & sel[1:0]). I have attached the simulation results below for your reference.

    This is the .info file I am using: 

    .in
    .tfall 0.1p
    .trise 0.1p
    .vih 1.8
    .vil 0
    .alias clk clk
    .alias reset reset
    .alias Out Out
    .alias d<3:0> {d[3] d[2] d[1] d[0]}
    .alias sel<1:0> {sel[1] sel[0]}

  • in reply to VK202409108412

    Your info file is wrong. It should be:

    .in clk reset d[*] sel[*]
.tfall 0.1p
.trise 0.1p
.vih 1.8
.vil 0
.alias clk clk
.alias reset reset
.alias Out Out
.alias d[*] d<*>
.alias sel[*] sel<*>

    This produces:

    Andrew

  • in reply to Andrew Beckett

    Thank you sir, it worked. Alternatively I have made it work by changing the .vcd file:

    $timescale
    1ps
    $end


    $scope module dff_mux $end
    $var wire 1 ! clk $end
    $var wire 4 " d [3:0] $end
    $var wire 1 # reset $end
    $var wire 2 $ sel [1:0] $end
    $upscope $end

    $enddefinitions $end
    #0
    $dumpvars
    0!
    b0 "
    1#
    b0 $
    $end
    #5000
    1!
    #10000
    0!
    0#
    #15000
    1!
    #20000
    0!
    b1010 "
    #25000
    1!
    #30000
    0!
    #35000
    1!
    #40000
    0!
    b1 $
    #45000
    1!
    #50000
    0!
    #55000
    1!
    #60000
    0!
    b10 $
    #65000
    1!
    #70000
    0!
    b11 $
    #75000
    1!
    #80000
    0!
    b1100 "
    #85000
    1!
    #90000
    0!
    b0 $
    #95000
    1!
    #100000
    0!
    b1 $
    #105000
    1!
    #110000
    0!
    b10 $
    #115000
    1!
    #120000
    0!
    b11 $
    #125000
    1!
    #130000
    0!
    #135000
    1!
    #140000
    0!
    b0 $
    #145000
    1!
    #150000
    0!
    b1 $
    #155000
    1!
    #160000
    0!
    b10 $
    #165000
    1!
    #170000
    0!
    b11 $
    #175000
    1!
    #180000
    0!
    #185000
    1!
    #190000

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