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  3. 3 terminal currents from 3 ideal components don't add up...

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3 terminal currents from 3 ideal components don't add up to meet KCL

a048
a048 5 months ago

Hello,

This circuit below has one vpulse generating a 50%/50% square wave between 0 and 1V with pulse width set to 0.5us-20ps. When Vin=0V, the top ideal current source turns on and sources 10nS*1V=10nA of current from the ideal cap, and the bottom ideal current source sinks 0A of current. When Vin=1V, the bottom ideal current source turns on and sinks 10nS*1V=10nA of current from the ideal cap, and the top ideal current source sources 0A of current. 

But the simulation waveforms show cap current incorrectly? pulsating between 10nA-0.5pA and -10nA-0.5pA while two ideal current source currents are correctly pulsating between 0 and 10nA/-10nA respectively. Adding these 3 terminal currents from 3 ideal components gives constant -0.5pA of current (instead of the expected 0A), which doesn't meet KCL. As a result, cap voltage keeps dropping while two ideal currents are practically sourcing/sinking equal amount of 10nA over time.

Is this a simulation error/artifact? Mainly concerned about the unsatisfied KCL principle despite of the simple setup.

Thanks

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  • a048
    a048 5 months ago

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  • Andrew Beckett
    Andrew Beckett 5 months ago in reply to a048

    I suspect this is either a gmin or an iabstol issue (since the currents are small) but I must have made a mistake when putting together the example based on your pictures as I'm not getting waveforms that match yours - so it's harder for me to explain. I can't spend too long trying to figure out what I've done wrong (or if there's something wrong in your description).

    Could you please use Simulation->Netlist->Display and then paste the input.scs contents here (not as an image though, as the text)? 

    Thanks,

    Andrew

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  • a048
    a048 5 months ago in reply to Andrew Beckett

    Hi, Andrew.

    Thanks very much for looking into this. I have attached input.scs below with model library file/Library name/nportirfiledir path omitted, and can provide more information if needed.

    Please kindly help take a look.

    Regards

    parameters BVP_DIO_WELL_LBC9=0 BVP_LBC9=0 ENABLE_ASSERT_2P0=1 \
    AOC_ASSERTS_HVDT_LBC9=0 AOC_ASSERTS_SMM_LBC9=0 \
    AOC_ASSERTS_POWER_LV_LBC9=0 REL_ASSERTS_METDCU_LBC9=1 cycle_time=10f \
    life_time=100K FREQ=1M gm_cp=10n tr=20p trf=20p vdd=1 vdd11=1

    // Library name: 
    // Cell name: sim_loop
    // View name: schematic
    G1 (vctl AVSS Vin AVSS) vccs gm=gm_cp
    G0 (AVDD vctl AVDD Vin) vccs gm=gm_cp
    C0 (vctl AVSS) capacitor c=20f
    V0 (Vin AVSS) vsource type=pulse val0=0 val1=1 period=100.0n rise=tr \
    fall=tr width=0.05u-tr
    V18 (AVSS 0) vsource dc=0 type=dc
    V5 (AVDD AVSS) vsource dc=vdd type=dc
    ic vctl=0.51
    simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1e-6 gmin=1e-12 \
    rforce=1 rabsshort=0 nportirreuse=yes \
    nportirfiledir=
    maxnotes=100 maxwarns=100 maxwarnstologfile=100 maxnotestologfile=100 \
    digits=5 cols=80 pivrel=1e-3 rebuild_matrix=yes \
    sensfile="../psf/sens.output" dochecklimit=yes \
    warning_id=[SPECTRE-16462 SPECTRE-16460 SPECTRE-17008 SPECTRE-17514 \
    CMI-2377 SFE-3232] warning_limit=0 warning_id=[SPECTRE-17074 \
    SPECTRE-17579] warning_change_severity=warning bin_relref=yes
    tranCheckLimit checklimit checkallasserts=yes severity=none
    tran tran stop=20m errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" saveclock=3600 method=gear2only \
    relref=sigglobal annotate=status maxiters=5
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts where=rawfile
    asserts info what=assert where=rawfile
    save Vin vctl C0:1 G0:sink G1:sink
    saveOptions options save=selected

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  • Andrew Beckett
    Andrew Beckett 5 months ago in reply to a048

    It was the initial condition on vctrl that I was missing (you didn't mention that).

    The reason for what you are seeing is that to aid convergence, a gmin conductance (1e-12 Siemens, i.e. 1TOhm) is added from the capacitor to ground to ensure a conductance path. This accounts for the 500fA current you are seeing (your initial condition voltage flowing through the gmin conductance). If you set gmin to (say) 1e-15 then you will see it reduce by 3 orders of magnitude.

    gmin is set to a value that usually would be an insignificant leakage path in real circuits, and the goal is to help with ensuring convergence. If nodes are truly floating then there's no single solution to the circuit equations, which makes convergence difficult - you have an ill-conditioned matrix to solve. So be wary of setting it too small in real circuits as this could lead to convergence difficulties.

    Note too that KCL is part of the convergence criteria, but there's still an acceptable tolerance to it (convergence is reached if the sum of currents < |largest current|*retol+iabstol - so the absolute tolerance is 1pA anyway. If you're trying to resolve tiny currents you might also need to reduce iabstol. However, usually the convergence will be beyond the absolute tolerances by virtue of other things affecting convergence.

    Hope that helps!

    Andrew

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  • a048
    a048 5 months ago in reply to Andrew Beckett

    I see. Thanks for the explanations. That was very helpful!

    Regards

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