Cadence simulation

I don't understand the question. What do you mean by CUT? Or by "output side of this"? Which tool are you using?

Andrew

CUT is circuit under test. I am using cadence virtuoso 45nm technology software and  when I test propagation delay of full adder,  I am using test bench which is design by input buffers at each full adder inputs and at the output of full adder (sum and carry) used the inverter then load capacitance at output. So my question is that how to decide load capacitance at buffer and inverter. 

CUT is circuit under test and I am using cadence virtuoso 45nm technology. When I test propagation delay of full adder then I used simulation environment testbench which is design with buffers at each inputs of full adder and inverter at output of full adder (sum and carry) and then total capacitance. So my question is that how to decide the value of load capacitance at buffers and at inverter.