import verilog

I import a gate level netlist to a schematic library.
We use integrated function in cadence: File/Import/Verilog
In the verilog code, the power lines VDD and VSS are connected to all gates:

...
supply1 VDD ;
supply0 VSS ;

SFFQX05TAR7 dtc_reg ( .D ( n9 ) , .TD ( dftopt13 ) , .SEL ( SE ) ,
.CK ( CLK ) , .Q ( SO ) , .VCCK ( VDD ) , .GNDK ( VSS ) ) ;

...

The import tool turns the power lines into global nets VDD! and VSS!.
Pins are created with naming accordingly: VDD! VSS!.
We prefer to avoid these global nets and want a digital cell with power nets and pins maintained like in the source code: VDD VSS.
How to set the GUI form such that the power names are maintained? (see GUI snapshot below)
Is there perhaps an alternative tool for converting the verilog code into schematics & symbols.

, Maikel Sturkenboom