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Cadence LVS Error in the Schematic vs Layout

ranaya

Hi All,

I am trying to perform LVS between a custom standard cell schematic and layout. I have the schematic, layout and the symbol views to this cell and when running the LVS, I run into the following error.

ERROR (OSSHNL-116): Cannot descend into any of the views defined in the view list 'cdl schematic' specified for library 'umc65ll' and cell 'N_12_LLRVT' for the instance 'MN0' in cell 'UMC65_DEV/umc65_rvt_inv1r_inwe/schematic'. Add one of these views or modify the view list so that it contains an existing view.

However, the cell MOSFET level components from the PDK are readily available and their schematic view is there already. So basically, from the cell we can descend into the transistor models. 

So actually what does this mean  ?

Thanks in advance

Anuradha

  • Anuradha,

    The fact that it appears to be trying to use the "cdl" views rather than "auCdl" suggests that it is trying to use the "digital" CDL netlister rather than the (more likely) "analog" CDL netlister (the difference is historical). Most PDKs are set up fro the analog netlister.

    Before starting Virtuoso, set:

    setenv CDS_Netlisting_Mode "Analog"

    or

    export CDS_Netlisting_Mode=Analog

    depending on whether you're using csh (the setenv line) or bash/ksh or similar (the export line).

    Then it should use the auCdl netlister. You didn't mention which LVS tool you're using, but it's likely to be using one of the Virtuoso netlisters anyway.

    Andrew

  • in reply to Andrew Beckett

    Dear Andrew, 

    Thanks for your quick answer. When migrating from old IC6 to new 2023 version, I have completely forgotten about the export variables. 

    export CDS_Netlisting_Mode=Analog solved the issue !

    Anuradha

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