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IC problem in simulation

RA202502215244

hi,

I'm trying to run transient simulation on my design. from some reason when simulation starts, all internal design terminals are starting from DC level 0(even pre-post inverter) and then spiking up sharply(few fs/as slope) before starting to converge to correct voltage.

does anyone knows what possibly could be the reason for that? 

  • Have you set any unusual options on the transient analysis, such as skipdc=yes? (I might expect skipdc=yes to have this kind of behaviour) Perhaps you can post the analysis statements from the bottom of your input.scs file so that we can see how the simulation has been set up?

    Andrew

  • in reply to Andrew Beckett

    hi Andrew,

    no, i didn't set skipdc=yes. you can see simulator options below(i hope photo is visible):

    however, i just find out that the IC are distorted because a verilog cell(with CDF parameters) which i'm using in my TB. while removing it from netlist the problem solved.

    anyway, it's strange because in previous virtuoso versions it did work with no issues...

    is there any root cause why a verilog cell can distort the initial conditions of all the DUT terminals?

    Thx

  • in reply to RA202502215244

    This won't be dependent upon the Virtuoso version - possibly the Spectre version though. If you have a Verilog-A model in there, maybe something is wrong with that - but it's going to be very hard to tell without seeing it.

    I suggest you contact customer support by logging into http://ask.cadence.com and then using the Case menu to submit a support case. Then one of the team can take a look at this with you.

    Andrew

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