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Hierarchical LVS Issues or how to deal with LVS hierarchy

spatz 2 months ago

IC6.1.8-64b.500.27
PVS 21.12

I have one main cell X and two subcells, A and B. Subcell A is instantiated twice.

Each subcell and the main cell has schematic, layout and symbol. Every subcell is DRC and LVS clean.

Now, when I perform LVS on the main cell X, PVS throws errors:

Mismatched Nets
Mismatched Instances
Mismatched Instance Parameters

In LVS Run Submission Form > LVS Options > Text and Connect I have enabled Connect by Name, the other options are default.

So I want to ask a more general questions:

Do I have to choose specific options to make it work?
Is there a tutorial about hiearchical design?
Is there a specific chapter in the documentation which I missed?
Can you share some tips?
What are the best practices?

Thank you!

RobMan 2 months ago

Part of the design process is debugging LVS. Can you identify what the issue is?

It's unlikely there is a real issue (assuming top level is connected correctly) but there is not enough information here to help.
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CSCNalu 2 months ago

This is really vague and i don't know how your PDK is set up, but a thing I end up checking first every time is making sure that the pins are both defined and placed properly (the pin covers metal entirely and the names are correct, case sensitive, etc)
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RobMan 2 months ago in reply to CSCNalu

Remember PVS will use the pin labels as correspondence points. Not the Virtuoso pin shapes (primarily for XL connectivity extraction). However, if your sub-cells are clean I assume you are familiar with this.
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